AR5K_REG_WRITE 216 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY(0x34), 0x00001c16); AR5K_REG_WRITE 218 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY(0x20), 0x00010000); AR5K_REG_WRITE 246 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_RC, val); AR5K_REG_WRITE 265 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG); AR5K_REG_WRITE 297 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_FC, AR5K_REG_WRITE 362 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); AR5K_REG_WRITE 403 dev/ic/ar5210.c AR5K_REG_WRITE(ar5210_ini[i].ini_register, AR5K_REG_WRITE 415 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE); AR5K_REG_WRITE 424 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); AR5K_REG_WRITE 514 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); AR5K_REG_WRITE 515 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, pcu_reg | high_id); AR5K_REG_WRITE 516 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BCR, beacon_reg); AR5K_REG_WRITE 544 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon & ~AR5K_AR5210_BEACON_EN); AR5K_REG_WRITE 557 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE); AR5K_REG_WRITE 575 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, AR5K_REG_WRITE 579 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, AR5K_REG_WRITE 585 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, AR5K_REG_WRITE 594 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_RFSTG, AR5K_AR5210_PHY_RFSTG_DISABLE); AR5K_REG_WRITE 602 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_SIG, phy_sig); AR5K_REG_WRITE 603 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_AGCCOARSE, phy_agc); AR5K_REG_WRITE 604 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PHY_ADCSAT, phy_sat); AR5K_REG_WRITE 617 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BEACON, beacon); AR5K_REG_WRITE 711 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TRIG_LVL, trigger_level); AR5K_REG_WRITE 809 dev/ic/ar5210.c AR5K_REG_WRITE((u_int32_t)initial[i].mode_register, AR5K_REG_WRITE 858 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_RETRY_LMT, AR5K_REG_WRITE 916 dev/ic/ar5210.c AR5K_REG_WRITE(tx_reg, phys_addr); AR5K_REG_WRITE 946 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BSR, AR5K_REG_WRITE 952 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BSR, AR5K_REG_WRITE 962 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); AR5K_REG_WRITE 988 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BSR, 0); AR5K_REG_WRITE 996 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CR, tx_queue); AR5K_REG_WRITE 1183 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_RXDP, phys_addr); AR5K_REG_WRITE 1189 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXE); AR5K_REG_WRITE 1197 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CR, AR5K_AR5210_CR_RXD); AR5K_REG_WRITE 1227 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL0, filter0); AR5K_REG_WRITE 1228 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_MCAST_FIL1, filter1); AR5K_REG_WRITE 1280 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_RX_FILTER, filter); AR5K_REG_WRITE 1502 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_STA_ID0, low_id); AR5K_REG_WRITE 1503 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, high_id); AR5K_REG_WRITE 1555 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_PCICFG, led); AR5K_REG_WRITE 1569 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BSS_ID0, low_id); AR5K_REG_WRITE 1570 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BSS_ID1, high_id | AR5K_REG_WRITE 1598 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, AR5K_REG_WRITE 1611 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, AR5K_REG_WRITE 1643 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_GPIODO, data); AR5K_REG_WRITE 1665 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_GPIOCR, AR5K_REG_WRITE 1738 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_SLOT_TIME, AR5K_REG_WRITE 1821 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), 0); AR5K_REG_WRITE 1883 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_OFF(entry, i), key_v[i]); AR5K_REG_WRITE 1906 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE 1907 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_KEYTABLE_MAC1(entry), high_id); AR5K_REG_WRITE 1931 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_REG_WRITE 1939 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_REG_WRITE 1949 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_AR5210_SCR_SLE_WAKE); AR5K_REG_WRITE 1959 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_SCR, AR5K_REG_WRITE 1977 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_STA_ID1, staid); AR5K_REG_WRITE 2056 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER0, next_beacon); AR5K_REG_WRITE 2057 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER1, timer1); AR5K_REG_WRITE 2058 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER2, timer2); AR5K_REG_WRITE 2059 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER3, timer3); AR5K_REG_WRITE 2061 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BEACON, interval & AR5K_REG_WRITE 2090 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CFP_PERIOD, cfp_period); AR5K_REG_WRITE 2091 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_CFP_DUR, state->bs_cfp_max_duration); AR5K_REG_WRITE 2092 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER2, AR5K_REG_WRITE 2104 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER0, state->bs_next_beacon); AR5K_REG_WRITE 2109 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_REG_WRITE 2132 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TIMER0, 0); AR5K_REG_WRITE 2139 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BEACON, AR5K_AR5210_BEACON_PERIOD); AR5K_REG_WRITE 2161 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_TXDP1, (u_int32_t)phys_addr); AR5K_REG_WRITE 2162 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_BCR, AR5K_REG_WRITE 2232 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); AR5K_REG_WRITE 2254 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_IMR, int_mask); AR5K_REG_WRITE 2261 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); AR5K_REG_WRITE 2302 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE); AR5K_REG_WRITE 2312 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_IER, AR5K_AR5210_IER_ENABLE); AR5K_REG_WRITE 2365 dev/ic/ar5210.c AR5K_REG_WRITE(AR5K_AR5210_EEPROM_BASE + (4 * offset), data); AR5K_REG_WRITE 246 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_RC, val); AR5K_REG_WRITE 263 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); AR5K_REG_WRITE 333 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); AR5K_REG_WRITE 336 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); AR5K_REG_WRITE 337 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); AR5K_REG_WRITE 354 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); AR5K_REG_WRITE 357 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 366 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); AR5K_REG_WRITE 369 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); AR5K_REG_WRITE 375 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 412 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); AR5K_REG_WRITE 477 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 489 dev/ic/ar5211.c AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, AR5K_REG_WRITE 503 dev/ic/ar5211.c AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, AR5K_REG_WRITE 537 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, AR5K_REG_WRITE 539 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, AR5K_REG_WRITE 546 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), AR5K_REG_WRITE 557 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), AR5K_REG_WRITE 577 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); AR5K_REG_WRITE 578 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); AR5K_REG_WRITE 580 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); AR5K_REG_WRITE 581 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); AR5K_REG_WRITE 589 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); AR5K_REG_WRITE 590 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); AR5K_REG_WRITE 609 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); AR5K_REG_WRITE 672 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); AR5K_REG_WRITE 713 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); AR5K_REG_WRITE 714 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); AR5K_REG_WRITE 922 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), AR5K_REG_WRITE 944 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), AR5K_REG_WRITE 953 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_WRITE 957 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), AR5K_REG_WRITE 970 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), AR5K_REG_WRITE 977 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), AR5K_REG_WRITE 989 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), AR5K_REG_WRITE 994 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), AR5K_REG_WRITE 1014 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), AR5K_REG_WRITE 1045 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SIMR0, AR5K_REG_WRITE 1048 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SIMR1, AR5K_REG_WRITE 1050 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SIMR2, AR5K_REG_WRITE 1079 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); AR5K_REG_WRITE 1125 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); AR5K_REG_WRITE 1290 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); AR5K_REG_WRITE 1296 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); AR5K_REG_WRITE 1304 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); AR5K_REG_WRITE 1334 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); AR5K_REG_WRITE 1335 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); AR5K_REG_WRITE 1380 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); AR5K_REG_WRITE 1597 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); AR5K_REG_WRITE 1598 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); AR5K_REG_WRITE 1671 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); AR5K_REG_WRITE 1672 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | AR5K_REG_WRITE 1681 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_REG_WRITE 1704 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, AR5K_REG_WRITE 1717 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, AR5K_REG_WRITE 1749 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); AR5K_REG_WRITE 1771 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, AR5K_REG_WRITE 1845 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); AR5K_REG_WRITE 1926 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); AR5K_REG_WRITE 1988 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); AR5K_REG_WRITE 2011 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE 2012 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); AR5K_REG_WRITE 2036 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_REG_WRITE 2044 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_REG_WRITE 2054 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); AR5K_REG_WRITE 2064 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_REG_WRITE 2082 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); AR5K_REG_WRITE 2155 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); AR5K_REG_WRITE 2156 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); AR5K_REG_WRITE 2157 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); AR5K_REG_WRITE 2158 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); AR5K_REG_WRITE 2160 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & AR5K_REG_WRITE 2189 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); AR5K_REG_WRITE 2190 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); AR5K_REG_WRITE 2191 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER2, AR5K_REG_WRITE 2203 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); AR5K_REG_WRITE 2208 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_REG_WRITE 2234 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); AR5K_REG_WRITE 2241 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); AR5K_REG_WRITE 2325 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); AR5K_REG_WRITE 2357 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); AR5K_REG_WRITE 2363 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); AR5K_REG_WRITE 2430 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); AR5K_REG_WRITE 2433 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, AR5K_REG_WRITE 2438 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, AR5K_REG_WRITE 2444 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); AR5K_REG_WRITE 2466 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); AR5K_REG_WRITE 2499 dev/ic/ar5211.c AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); AR5K_REG_WRITE 2570 dev/ic/ar5211.c AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, AR5K_REG_WRITE 249 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RC, val); AR5K_REG_WRITE 266 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_CFG, AR5K_AR5212_INIT_CFG); AR5K_REG_WRITE 345 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_PLL, clock); AR5K_REG_WRITE 348 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_MODE, mode); AR5K_REG_WRITE 349 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TURBO, turbo); AR5K_REG_WRITE 366 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_2GHZ); AR5K_REG_WRITE 369 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 378 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0x34), 0x00001c16); AR5K_REG_WRITE 381 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0x20), 0x00010000); AR5K_REG_WRITE 387 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 429 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_DISABLE); AR5K_REG_WRITE 517 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0), AR5K_AR5212_PHY_SHIFT_5GHZ); AR5K_REG_WRITE 535 dev/ic/ar5212.c AR5K_REG_WRITE((u_int32_t)ar5212_mode[i].mode_register, AR5K_REG_WRITE 553 dev/ic/ar5212.c AR5K_REG_WRITE((u_int32_t)ar5212_ini[i].ini_register, AR5K_REG_WRITE 574 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code), AR5K_REG_WRITE 583 dev/ic/ar5212.c AR5K_REG_WRITE(data, AR5K_REG_WRITE 587 dev/ic/ar5212.c AR5K_REG_WRITE(data + AR5K_REG_WRITE 598 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL, AR5K_REG_WRITE 604 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data); AR5K_REG_WRITE 668 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0, AR5K_REG_WRITE 670 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1, AR5K_REG_WRITE 678 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0x5a), AR5K_REG_WRITE 689 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY(0x0d), AR5K_REG_WRITE 715 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_SEQNUM(0), s_seq); AR5K_REG_WRITE 716 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, s_ant); AR5K_REG_WRITE 718 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, s_led[1]); AR5K_REG_WRITE 719 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIODO, s_led[2]); AR5K_REG_WRITE 727 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PISR, 0xffffffff); AR5K_REG_WRITE 728 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES); AR5K_REG_WRITE 747 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_ACTIVE, AR5K_AR5212_PHY_ENABLE); AR5K_REG_WRITE 800 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SCR, AR5K_AR5212_PHY_SCR_32MHZ); AR5K_REG_WRITE 801 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SLMT, AR5K_AR5212_PHY_SLMT_32MHZ); AR5K_REG_WRITE 802 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SCAL, AR5K_AR5212_PHY_SCAL_32MHZ); AR5K_REG_WRITE 803 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SCLOCK, AR5K_AR5212_PHY_SCLOCK_32MHZ); AR5K_REG_WRITE 804 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ); AR5K_REG_WRITE 805 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_radio == AR5K_AR5111 ? AR5K_REG_WRITE 820 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DEFAULT_ANTENNA, ant); AR5K_REG_WRITE 861 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); AR5K_REG_WRITE 862 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, pcu_reg | high_id); AR5K_REG_WRITE 904 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_PAPD_PROBE, AR5K_REG_WRITE 1081 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_RETRY_LMT(queue), AR5K_REG_WRITE 1103 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_LCL_IFS(queue), AR5K_REG_WRITE 1112 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_WRITE 1116 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_CBRCFG(queue), AR5K_REG_WRITE 1129 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), AR5K_REG_WRITE 1136 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_CHAN_TIME(queue), AR5K_REG_WRITE 1148 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), AR5K_REG_WRITE 1153 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_MISC(queue), AR5K_REG_WRITE 1173 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_RDYTIMECFG(queue), AR5K_REG_WRITE 1204 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SIMR0, AR5K_REG_WRITE 1207 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SIMR1, AR5K_REG_WRITE 1209 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SIMR2, AR5K_REG_WRITE 1238 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_TXDP(queue), phys_addr); AR5K_REG_WRITE 1284 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0); AR5K_REG_WRITE 1521 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RXDP, phys_addr); AR5K_REG_WRITE 1527 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXE); AR5K_REG_WRITE 1535 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_CR, AR5K_AR5212_CR_RXD); AR5K_REG_WRITE 1565 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL0, filter0); AR5K_REG_WRITE 1566 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_MCAST_FIL1, filter1); AR5K_REG_WRITE 1638 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_RX_FILTER, filter & 0xff); AR5K_REG_WRITE 1639 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_ERR_FIL, data); AR5K_REG_WRITE 1879 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_STA_ID0, low_id); AR5K_REG_WRITE 1880 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, high_id); AR5K_REG_WRITE 1951 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, 0xfffffff); AR5K_REG_WRITE 1952 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, 0xfffffff); AR5K_REG_WRITE 1959 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_ID0, low_id); AR5K_REG_WRITE 1960 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_ID1, high_id | AR5K_REG_WRITE 1969 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_REG_WRITE 1987 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM0, low_id); AR5K_REG_WRITE 1988 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BSS_IDM1, high_id); AR5K_REG_WRITE 1999 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, AR5K_REG_WRITE 2012 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, AR5K_REG_WRITE 2044 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIODO, data); AR5K_REG_WRITE 2066 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_GPIOCR, AR5K_REG_WRITE 2129 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_TX, 0); AR5K_REG_WRITE 2130 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RX, 0); AR5K_REG_WRITE 2131 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_RXCLR, 0); AR5K_REG_WRITE 2132 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PROFCNT_CYCLE, 0); AR5K_REG_WRITE 2180 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time); AR5K_REG_WRITE 2261 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), 0); AR5K_REG_WRITE 2264 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_TYPE(entry), AR5K_REG_WRITE 2327 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_OFF(entry, i), key_v[i]); AR5K_REG_WRITE 2350 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC0(entry), low_id); AR5K_REG_WRITE 2351 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_KEYTABLE_MAC1(entry), high_id); AR5K_REG_WRITE 2375 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_REG_WRITE 2383 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_REG_WRITE 2393 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_AR5212_SCR_SLE_WAKE); AR5K_REG_WRITE 2403 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SCR, AR5K_REG_WRITE 2421 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_STA_ID1, staid); AR5K_REG_WRITE 2494 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER0, next_beacon); AR5K_REG_WRITE 2495 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER1, timer1); AR5K_REG_WRITE 2496 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER2, timer2); AR5K_REG_WRITE 2497 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER3, timer3); AR5K_REG_WRITE 2499 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BEACON, interval & AR5K_REG_WRITE 2530 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_CFP_PERIOD, cfp_period); AR5K_REG_WRITE 2531 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_CFP_DUR, state->bs_cfp_max_duration); AR5K_REG_WRITE 2532 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER2, AR5K_REG_WRITE 2543 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER0, state->bs_next_beacon); AR5K_REG_WRITE 2548 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_REG_WRITE 2584 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SLEEP0, AR5K_REG_WRITE 2590 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SLEEP1, AR5K_REG_WRITE 2594 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_SLEEP2, AR5K_REG_WRITE 2605 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_TIMER0, 0); AR5K_REG_WRITE 2612 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_BEACON, AR5K_AR5212_BEACON_PERIOD); AR5K_REG_WRITE 2699 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); AR5K_REG_WRITE 2731 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PIMR, int_mask); AR5K_REG_WRITE 2737 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); AR5K_REG_WRITE 2805 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_DISABLE); AR5K_REG_WRITE 2808 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, AR5K_REG_WRITE 2813 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_RADAR, AR5K_REG_WRITE 2819 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_IER, AR5K_AR5212_IER_ENABLE); AR5K_REG_WRITE 2841 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset); AR5K_REG_WRITE 2874 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_EEPROM_BASE, (u_int8_t)offset - 1); AR5K_REG_WRITE 2915 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_PCDAC_TXPOWER(i), AR5K_REG_WRITE 2921 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE1, AR5K_REG_WRITE 2925 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE2, AR5K_REG_WRITE 2929 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE3, AR5K_REG_WRITE 2933 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE4, AR5K_REG_WRITE 2938 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, AR5K_REG_WRITE 2942 dev/ic/ar5212.c AR5K_REG_WRITE(AR5K_AR5212_PHY_TXPOWER_RATE_MAX, AR5K_REG_WRITE 1604 dev/ic/ar5xxx.c AR5K_REG_WRITE(ar5111_rf[i].rf_register, rf[i]); AR5K_REG_WRITE 1696 dev/ic/ar5xxx.c AR5K_REG_WRITE(ar5112_rf[i].rf_register, rf[i]); AR5K_REG_WRITE 1724 dev/ic/ar5xxx.c AR5K_REG_WRITE((u_int32_t)ar5k_rfg[i].rfg_register, AR5K_REG_WRITE 1372 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \ AR5K_REG_WRITE 1375 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags)) AR5K_REG_WRITE 1377 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags)) AR5K_REG_WRITE 1379 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags)) AR5K_REG_WRITE 1382 dev/ic/ar5xxx.h AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val) AR5K_REG_WRITE 1403 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, (1 << _queue))