AR5K_REG_READ 208 dev/ic/ar5210.c srev = AR5K_REG_READ(AR5K_AR5210_SREV);
AR5K_REG_READ 212 dev/ic/ar5210.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5210_PHY_CHIP_ID) &
AR5K_REG_READ 220 dev/ic/ar5210.c (ar5k_bitswap((AR5K_REG_READ(AR5K_AR5210_PHY(256) >> 28) & 0xf), 4)
AR5K_REG_READ 398 dev/ic/ar5210.c AR5K_REG_READ(ar5210_ini[i].ini_register);
AR5K_REG_READ 543 dev/ic/ar5210.c beacon = AR5K_REG_READ(AR5K_AR5210_BEACON);
AR5K_REG_READ 570 dev/ic/ar5210.c phy_sig = AR5K_REG_READ(AR5K_AR5210_PHY_SIG);
AR5K_REG_READ 571 dev/ic/ar5210.c phy_agc = AR5K_REG_READ(AR5K_AR5210_PHY_AGCCOARSE);
AR5K_REG_READ 572 dev/ic/ar5210.c phy_sat = AR5K_REG_READ(AR5K_AR5210_PHY_ADCSAT);
AR5K_REG_READ 666 dev/ic/ar5210.c noise_floor = AR5K_REG_READ(AR5K_AR5210_PHY_NF);
AR5K_REG_READ 698 dev/ic/ar5210.c trigger_level = AR5K_REG_READ(AR5K_AR5210_TRIG_LVL);
AR5K_REG_READ 890 dev/ic/ar5210.c return (AR5K_REG_READ(tx_reg));
AR5K_REG_READ 934 dev/ic/ar5210.c tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
AR5K_REG_READ 974 dev/ic/ar5210.c tx_queue = AR5K_REG_READ(AR5K_AR5210_CR);
AR5K_REG_READ 1177 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_RXDP));
AR5K_REG_READ 1203 dev/ic/ar5210.c i > 0 && (AR5K_REG_READ(AR5K_AR5210_CR) & AR5K_AR5210_CR_RXE) != 0;
AR5K_REG_READ 1266 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_RX_FILTER));
AR5K_REG_READ 1389 dev/ic/ar5210.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5210_##_x));
AR5K_REG_READ 1532 dev/ic/ar5210.c led = AR5K_REG_READ(AR5K_AR5210_PCICFG);
AR5K_REG_READ 1599 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
AR5K_REG_READ 1612 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &~ AR5K_AR5210_GPIOCR_ALL(gpio))
AR5K_REG_READ 1625 dev/ic/ar5210.c return (((AR5K_REG_READ(AR5K_AR5210_GPIODI) &
AR5K_REG_READ 1638 dev/ic/ar5210.c data = AR5K_REG_READ(AR5K_AR5210_GPIODO);
AR5K_REG_READ 1660 dev/ic/ar5210.c data = (AR5K_REG_READ(AR5K_AR5210_GPIOCR) &
AR5K_REG_READ 1677 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_TSF_L32));
AR5K_REG_READ 1683 dev/ic/ar5210.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5210_TSF_U32);
AR5K_REG_READ 1684 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_TSF_L32) | (tsf << 32));
AR5K_REG_READ 1719 dev/ic/ar5210.c statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5210_ACK_FAIL);
AR5K_REG_READ 1720 dev/ic/ar5210.c statistics->rts_bad += AR5K_REG_READ(AR5K_AR5210_RTS_FAIL);
AR5K_REG_READ 1721 dev/ic/ar5210.c statistics->rts_good += AR5K_REG_READ(AR5K_AR5210_RTS_OK);
AR5K_REG_READ 1722 dev/ic/ar5210.c statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5210_FCS_FAIL);
AR5K_REG_READ 1723 dev/ic/ar5210.c statistics->beacons += AR5K_REG_READ(AR5K_AR5210_BEACON_CNT);
AR5K_REG_READ 1747 dev/ic/ar5210.c return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5210_SLOT_TIME) &
AR5K_REG_READ 1767 dev/ic/ar5210.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_REG_READ 1787 dev/ic/ar5210.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5210_TIME_OUT),
AR5K_REG_READ 1834 dev/ic/ar5210.c if (AR5K_REG_READ(AR5K_AR5210_KEYTABLE_MAC1(entry)) &
AR5K_REG_READ 1923 dev/ic/ar5210.c staid = AR5K_REG_READ(AR5K_AR5210_STA_ID1);
AR5K_REG_READ 1953 dev/ic/ar5210.c if ((AR5K_REG_READ(AR5K_AR5210_PCICFG) &
AR5K_REG_READ 2110 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_BEACON) &~
AR5K_REG_READ 2151 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_BSR) &
AR5K_REG_READ 2153 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_CR) &
AR5K_REG_READ 2178 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
AR5K_REG_READ 2186 dev/ic/ar5210.c if ((data = AR5K_REG_READ(AR5K_AR5210_ISR)) == HAL_INT_NOCARD) {
AR5K_REG_READ 2322 dev/ic/ar5210.c return (AR5K_REG_READ(AR5K_AR5210_CFG) & AR5K_AR5210_CFG_EEBS ?
AR5K_REG_READ 2337 dev/ic/ar5210.c (void)AR5K_REG_READ(AR5K_AR5210_EEPROM_BASE + (4 * offset));
AR5K_REG_READ 2341 dev/ic/ar5210.c status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
AR5K_REG_READ 2346 dev/ic/ar5210.c (AR5K_REG_READ(AR5K_AR5210_EEPROM_RDATA) & 0xffff);
AR5K_REG_READ 2369 dev/ic/ar5210.c status = AR5K_REG_READ(AR5K_AR5210_EEPROM_STATUS);
AR5K_REG_READ 204 dev/ic/ar5210var.h (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C, \
AR5K_REG_READ 205 dev/ic/ar5210var.h (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 }, \
AR5K_REG_READ 211 dev/ic/ar5211.c srev = AR5K_REG_READ(AR5K_AR5211_SREV);
AR5K_REG_READ 215 dev/ic/ar5211.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) &
AR5K_REG_READ 241 dev/ic/ar5211.c AR5K_REG_READ(AR5K_AR5211_RXDP);
AR5K_REG_READ 370 dev/ic/ar5211.c srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff;
AR5K_REG_READ 429 dev/ic/ar5211.c s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0));
AR5K_REG_READ 430 dev/ic/ar5211.c s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
AR5K_REG_READ 436 dev/ic/ar5211.c s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) &
AR5K_REG_READ 438 dev/ic/ar5211.c s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR);
AR5K_REG_READ 439 dev/ic/ar5211.c s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO);
AR5K_REG_READ 611 dev/ic/ar5211.c data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) &
AR5K_REG_READ 678 dev/ic/ar5211.c return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
AR5K_REG_READ 726 dev/ic/ar5211.c AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN)
AR5K_REG_READ 731 dev/ic/ar5211.c iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR);
AR5K_REG_READ 732 dev/ic/ar5211.c i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I);
AR5K_REG_READ 733 dev/ic/ar5211.c q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q);
AR5K_REG_READ 772 dev/ic/ar5211.c trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG),
AR5K_REG_READ 1064 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue)));
AR5K_REG_READ 1119 dev/ic/ar5211.c pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) &
AR5K_REG_READ 1284 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_RXDP));
AR5K_REG_READ 1310 dev/ic/ar5211.c i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0;
AR5K_REG_READ 1374 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER));
AR5K_REG_READ 1485 dev/ic/ar5211.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x));
AR5K_REG_READ 1682 dev/ic/ar5211.c (AR5K_REG_READ(AR5K_AR5211_BEACON) &
AR5K_REG_READ 1705 dev/ic/ar5211.c (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
AR5K_REG_READ 1718 dev/ic/ar5211.c (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
AR5K_REG_READ 1731 dev/ic/ar5211.c return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) &
AR5K_REG_READ 1744 dev/ic/ar5211.c data = AR5K_REG_READ(AR5K_AR5211_GPIODO);
AR5K_REG_READ 1766 dev/ic/ar5211.c data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &
AR5K_REG_READ 1783 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_TSF_L32));
AR5K_REG_READ 1789 dev/ic/ar5211.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32);
AR5K_REG_READ 1791 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32));
AR5K_REG_READ 1826 dev/ic/ar5211.c statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL);
AR5K_REG_READ 1827 dev/ic/ar5211.c statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL);
AR5K_REG_READ 1828 dev/ic/ar5211.c statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK);
AR5K_REG_READ 1829 dev/ic/ar5211.c statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL);
AR5K_REG_READ 1830 dev/ic/ar5211.c statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT);
AR5K_REG_READ 1853 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff);
AR5K_REG_READ 1872 dev/ic/ar5211.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
AR5K_REG_READ 1892 dev/ic/ar5211.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
AR5K_REG_READ 1939 dev/ic/ar5211.c if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) &
AR5K_REG_READ 2028 dev/ic/ar5211.c staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1);
AR5K_REG_READ 2058 dev/ic/ar5211.c if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) &
AR5K_REG_READ 2209 dev/ic/ar5211.c (AR5K_REG_READ(AR5K_AR5211_BEACON) &~
AR5K_REG_READ 2269 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
AR5K_REG_READ 2280 dev/ic/ar5211.c data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR);
AR5K_REG_READ 2454 dev/ic/ar5211.c return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ?
AR5K_REG_READ 2471 dev/ic/ar5211.c status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
AR5K_REG_READ 2476 dev/ic/ar5211.c (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff);
AR5K_REG_READ 2503 dev/ic/ar5211.c status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
AR5K_REG_READ 208 dev/ic/ar5212.c srev = AR5K_REG_READ(AR5K_AR5212_SREV);
AR5K_REG_READ 212 dev/ic/ar5212.c hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5212_PHY_CHIP_ID) &
AR5K_REG_READ 244 dev/ic/ar5212.c AR5K_REG_READ(AR5K_AR5212_RXDP);
AR5K_REG_READ 382 dev/ic/ar5212.c srev = (AR5K_REG_READ(AR5K_AR5212_PHY(0x100)) >> 24) & 0xff;
AR5K_REG_READ 447 dev/ic/ar5212.c s_seq = AR5K_REG_READ(AR5K_AR5212_DCU_SEQNUM(0));
AR5K_REG_READ 448 dev/ic/ar5212.c s_ant = AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
AR5K_REG_READ 454 dev/ic/ar5212.c s_led[0] = AR5K_REG_READ(AR5K_AR5212_PCICFG) &
AR5K_REG_READ 456 dev/ic/ar5212.c s_led[1] = AR5K_REG_READ(AR5K_AR5212_GPIOCR);
AR5K_REG_READ 457 dev/ic/ar5212.c s_led[2] = AR5K_REG_READ(AR5K_AR5212_GPIODO);
AR5K_REG_READ 749 dev/ic/ar5212.c data = AR5K_REG_READ(AR5K_AR5212_PHY_RX_DELAY) &
AR5K_REG_READ 826 dev/ic/ar5212.c return AR5K_REG_READ(AR5K_AR5212_DEFAULT_ANTENNA);
AR5K_REG_READ 874 dev/ic/ar5212.c AR5K_REG_READ(AR5K_AR5212_PHY_IQ) & AR5K_AR5212_PHY_IQ_RUN)
AR5K_REG_READ 879 dev/ic/ar5212.c iq_corr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_CORR);
AR5K_REG_READ 880 dev/ic/ar5212.c i_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_I);
AR5K_REG_READ 881 dev/ic/ar5212.c q_pwr = AR5K_REG_READ(AR5K_AR5212_PHY_IQRES_CAL_PWR_Q);
AR5K_REG_READ 929 dev/ic/ar5212.c trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TXCFG),
AR5K_REG_READ 1223 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_QCU_TXDP(queue)));
AR5K_REG_READ 1278 dev/ic/ar5212.c pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) &
AR5K_REG_READ 1515 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_RXDP));
AR5K_REG_READ 1541 dev/ic/ar5212.c i > 0 && (AR5K_REG_READ(AR5K_AR5212_CR) & AR5K_AR5212_CR_RXE) != 0;
AR5K_REG_READ 1607 dev/ic/ar5212.c filter = AR5K_REG_READ(AR5K_AR5212_RX_FILTER);
AR5K_REG_READ 1608 dev/ic/ar5212.c data = AR5K_REG_READ(AR5K_AR5212_PHY_ERR_FIL);
AR5K_REG_READ 1752 dev/ic/ar5212.c printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5212_##_x));
AR5K_REG_READ 1970 dev/ic/ar5212.c (AR5K_REG_READ(AR5K_AR5212_BEACON) &
AR5K_REG_READ 2000 dev/ic/ar5212.c (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))
AR5K_REG_READ 2013 dev/ic/ar5212.c (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &~ AR5K_AR5212_GPIOCR_ALL(gpio))
AR5K_REG_READ 2026 dev/ic/ar5212.c return (((AR5K_REG_READ(AR5K_AR5212_GPIODI) &
AR5K_REG_READ 2039 dev/ic/ar5212.c data = AR5K_REG_READ(AR5K_AR5212_GPIODO);
AR5K_REG_READ 2061 dev/ic/ar5212.c data = (AR5K_REG_READ(AR5K_AR5212_GPIOCR) &
AR5K_REG_READ 2078 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_TSF_L32));
AR5K_REG_READ 2084 dev/ic/ar5212.c u_int64_t tsf = AR5K_REG_READ(AR5K_AR5212_TSF_U32);
AR5K_REG_READ 2086 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_TSF_L32) | (tsf << 32));
AR5K_REG_READ 2122 dev/ic/ar5212.c statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5212_ACK_FAIL);
AR5K_REG_READ 2123 dev/ic/ar5212.c statistics->rts_bad += AR5K_REG_READ(AR5K_AR5212_RTS_FAIL);
AR5K_REG_READ 2124 dev/ic/ar5212.c statistics->rts_good += AR5K_REG_READ(AR5K_AR5212_RTS_OK);
AR5K_REG_READ 2125 dev/ic/ar5212.c statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5212_FCS_FAIL);
AR5K_REG_READ 2126 dev/ic/ar5212.c statistics->beacons += AR5K_REG_READ(AR5K_AR5212_BEACON_CNT);
AR5K_REG_READ 2146 dev/ic/ar5212.c data = AR5K_REG_READ(AR5K_AR5212_PHY_PAPD_PROBE);
AR5K_REG_READ 2188 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff);
AR5K_REG_READ 2207 dev/ic/ar5212.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
AR5K_REG_READ 2227 dev/ic/ar5212.c return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5212_TIME_OUT),
AR5K_REG_READ 2278 dev/ic/ar5212.c if (AR5K_REG_READ(AR5K_AR5212_KEYTABLE_MAC1(entry)) &
AR5K_REG_READ 2367 dev/ic/ar5212.c staid = AR5K_REG_READ(AR5K_AR5212_STA_ID1);
AR5K_REG_READ 2397 dev/ic/ar5212.c if ((AR5K_REG_READ(AR5K_AR5212_PCICFG) &
AR5K_REG_READ 2549 dev/ic/ar5212.c (AR5K_REG_READ(AR5K_AR5212_BEACON) &~
AR5K_REG_READ 2640 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
AR5K_REG_READ 2651 dev/ic/ar5212.c data = AR5K_REG_READ(AR5K_AR5212_RAC_PISR);
AR5K_REG_READ 2829 dev/ic/ar5212.c return (AR5K_REG_READ(AR5K_AR5212_CFG) & AR5K_AR5212_CFG_EEBS ?
AR5K_REG_READ 2846 dev/ic/ar5212.c status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS);
AR5K_REG_READ 2851 dev/ic/ar5212.c (AR5K_REG_READ(AR5K_AR5212_EEPROM_DATA) & 0xffff);
AR5K_REG_READ 2878 dev/ic/ar5212.c status = AR5K_REG_READ(AR5K_AR5212_EEPROM_STATUS);
AR5K_REG_READ 675 dev/ic/ar5xxx.c data = AR5K_REG_READ(reg);
AR5K_REG_READ 1372 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
AR5K_REG_READ 1375 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
AR5K_REG_READ 1377 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
AR5K_REG_READ 1379 dev/ic/ar5xxx.h AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
AR5K_REG_READ 1384 dev/ic/ar5xxx.h AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
AR5K_REG_READ 1400 dev/ic/ar5xxx.h (AR5K_REG_READ(_reg) & (1 << _queue)) \