1 /* $OpenBSD: amd756reg.h,v 1.1 2000/11/07 18:21:22 mickey Exp $ */
2 /* $NetBSD$ */
3
4 /*
5 * Copyright (c) 1999, by UCHIYAMA Yasushi
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. The name of the developer may NOT be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Register definitions for the AMD756 Peripheral Bus Controller.
31 */
32
33 /*
34 * Edge Triggered Interrupt Select register. (0x54)
35 * bits 7-4: reserved
36 * bit 3: Edge Triggered Interrupt Select for PCI Interrupt D
37 * bit 2: Edge Triggered Interrupt Select for PCI Interrupt C
38 * bit 1: Edge Triggered Interrupt Select for PCI Interrupt B
39 * bit 0: Edge Triggered Interrupt Select for PCI Interrupt A
40 * 0 = active Low and level triggered
41 * 1 = active High and edge triggered
42 *
43 * PIRQ Select register. (0x56-57)
44 * bits 15-12: PIRQD# Select
45 * bits 11-8: PIRQD# Select
46 * bits 7-4: PIRQD# Select
47 * bits 3-0: PIRQD# Select
48 * 0000: Reserved 0100: IRQ4 1000: Reserved 1100: IRQ12
49 * 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved
50 * 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14
51 * 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15
52 */
53 #define AMD756_CFG_PIR 0x54
54
55 #define AMD756_GET_EDGESEL(ph) \
56 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) & 0xff)
57
58 #define AMD756_GET_PIIRQSEL(ph) \
59 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) >> 16)
60
61 #define AMD756_SET_EDGESEL(ph, n) \
62 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
63 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
64 & 0xffff0000) | (n))
65
66 #define AMD756_SET_PIIRQSEL(ph, n) \
67 pci_conf_write((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR, \
68 (pci_conf_read((ph)->ph_pc, (ph)->ph_tag, AMD756_CFG_PIR) \
69 & 0x000000ff) | ((n) << 16))
70
71 #define AMD756_PIRQ_MASK 0xdefa
72 #define AMD756_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3)
73 #define AMD756_LEGAL_IRQ(irq) \
74 ((irq) >= 0 && (irq) <= 15 && ((1 << (irq)) & AMD756_PIRQ_MASK) != 0)
75