root/dev/pci/if_casreg.h

INCLUDED FROM

    1 /*      $OpenBSD: if_casreg.h,v 1.5 2007/04/22 12:20:42 kettenis Exp $  */
    3 /*
    4  *
    5  * Copyright (C) 2007 Mark Kettenis.
    6  * Copyright (C) 2001 Eduardo Horvath.
    7  * All rights reserved.
    8  *
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  */
   33 #ifndef _IF_CASREG_H
   34 #define _IF_CASREG_H
   36 /*
   37  * Register definitions for Sun Cassini ethernet controllers.
   38  */
   40 /*
   41  * First bank: this registers live at the start of the PCI
   42  * mapping, and at the start of the second bank of the SBUS
   43  * version.
   44  */
   45 #define CAS_SEB_STATE           0x0000  /* SEB state reg, R/O */
   46 #define CAS_CONFIG              0x0004  /* config reg */
   47 #define CAS_STATUS              0x000c  /* status reg */
   48 /* Note: Reading the status reg clears bits 0-6 */
   49 #define CAS_INTMASK             0x0010
   50 #define CAS_INTACK              0x0014  /* Interrupt acknowledge, W/O */
   51 #define CAS_STATUS_ALIAS        0x001c
   52 /* Note: Same as CAS_STATUS but reading it does not clear bits. */
   54 #define CAS_ERROR_STATUS        0x1000  /* PCI error status R/C */
   55 #define CAS_ERROR_MASK          0x0004
   56 #define CAS_BIF_CONFIG          0x0008  /* BIF config reg */
   57 #define CAS_BIF_DIAG            0x000c
   58 #define CAS_RESET               0x1010  /* Software reset register */
   60 /* Bits in CAS_SEB register */
   61 #define CAS_SEB_ARB             0x000000002     /* Arbitration status */
   62 #define CAS_SEB_RXWON           0x000000004
   64 /* Bits in CAS_CONFIG register */
   65 #define CAS_CONFIG_BURST_64     0x000000000     /* 0->infinity, 1->64KB */
   66 #define CAS_CONFIG_BURST_INF    0x000000001     /* 0->infinity, 1->64KB */
   67 #define CAS_CONFIG_TXDMA_LIMIT  0x00000003e
   68 #define CAS_CONFIG_RXDMA_LIMIT  0x0000007c0
   70 #define CAS_CONFIG_TXDMA_LIMIT_SHIFT    1
   71 #define CAS_CONFIG_RXDMA_LIMIT_SHIFT    6
   73 /* Top part of CAS_STATUS has TX completion information */
   74 #define CAS_STATUS_TX_COMPL     0xfff800000     /* TX completion reg. */
   76 /*
   77  * Interrupt bits, for both the CAS_STATUS and CAS_INTMASK regs.
   78  * Bits 0-6 auto-clear when read.
   79  */
   80 #define CAS_INTR_TX_INTME       0x000000001     /* Frame w/INTME bit set sent */
   81 #define CAS_INTR_TX_EMPTY       0x000000002     /* TX ring empty */
   82 #define CAS_INTR_TX_DONE        0x000000004     /* TX complete */
   83 #define CAS_INTR_TX_TAG_ERR     0x000000008
   84 #define CAS_INTR_RX_DONE        0x000000010     /* Got a packet */
   85 #define CAS_INTR_RX_NOBUF       0x000000020
   86 #define CAS_INTR_RX_TAG_ERR     0x000000040
   87 #define CAS_INTR_RX_COMP_FULL   0x000000080
   88 #define CAS_INTR_PCS            0x000002000     /* Physical Code Sub-layer */
   89 #define CAS_INTR_TX_MAC         0x000004000
   90 #define CAS_INTR_RX_MAC         0x000008000
   91 #define CAS_INTR_MAC_CONTROL    0x000010000     /* MAC control interrupt */
   92 #define CAS_INTR_MIF            0x000020000
   93 #define CAS_INTR_BERR           0x000040000     /* Bus error interrupt */
   94 #define CAS_INTR_BITS   "\020"                                  \
   95                         "\1INTME\2TXEMPTY\3TXDONE\4TX_TAG_ERR"  \
   96                         "\5RXDONE\6RXNOBUF\7RX_TAG_ERR"         \
   97                         "\10RX_COMP_FULL"                       \
   98                         "\16PCS\17TXMAC\20RXMAC"                \
   99                         "\21MACCONTROL\22MIF\23BERR"
  101 /* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */
  102 #define CAS_ERROR_STAT_BADACK   0x000000001     /* No ACK64# */
  103 #define CAS_ERROR_STAT_DTRTO    0x000000002     /* Delayed xaction timeout */
  104 #define CAS_ERROR_STAT_OTHERS   0x000000004
  106 /* CAS_BIF_CONFIG register bits */
  107 #define CAS_BIF_CONFIG_SLOWCLK  0x000000001     /* Parity error timing */
  108 #define CAS_BIF_CONFIG_HOST_64  0x000000002     /* 64-bit host */
  109 #define CAS_BIF_CONFIG_B64D_DIS 0x000000004     /* no 64-bit data cycle */
  110 #define CAS_BIF_CONFIG_M66EN    0x000000008
  112 /* CAS_RESET register bits -- TX and RX self clear when complete. */
  113 #define CAS_RESET_TX            0x000000001     /* Reset TX half */
  114 #define CAS_RESET_RX            0x000000002     /* Reset RX half */
  115 #define CAS_RESET_RSTOUT        0x000000004     /* Force PCI RSTOUT# */
  117 /* TX DMA registers */
  118 #define CAS_TX_CONFIG           0x2004
  120 #define CAS_TX_FIFO_WR_PTR      0x2014          /* FIFO write pointer */
  121 #define CAS_TX_FIFO_SDWR_PTR    0x2018          /* FIFO shadow write pointer */
  122 #define CAS_TX_FIFO_RD_PTR      0x201c          /* FIFO read pointer */
  123 #define CAS_TX_FIFO_SDRD_PTR    0x2020          /* FIFO shadow read pointer */
  124 #define CAS_TX_FIFO_PKT_CNT     0x2024          /* FIFO packet counter */
  126 #define CAS_TX_STATE_MACHINE    0x2028          /* ETX state machine reg */
  127 #define CAS_TX_DATA_PTR         0x2030          /* ETX state machine reg (64-bit)*/
  129 #define CAS_TX_KICK1            0x2038          /* Write last valid desc + 1 */
  130 #define CAS_TX_KICK2            0x203c
  131 #define CAS_TX_KICK3            0x2040
  132 #define CAS_TX_KICK4            0x2044
  133 #define CAS_TX_COMPLETION1      0x2048
  134 #define CAS_TX_COMPLETION2      0x204c
  135 #define CAS_TX_COMPLETION3      0x2050
  136 #define CAS_TX_COMPLETION4      0x2054
  137 #define CAS_TX_RING_PTR_LO1     0x2060
  138 #define CAS_TX_RING_PTR_HI1     0x2064
  139 #define CAS_TX_RING_PTR_LO2     0x2068
  140 #define CAS_TX_RING_PTR_HI2     0x206c
  141 #define CAS_TX_RING_PTR_LO3     0x2070
  142 #define CAS_TX_RING_PTR_HI3     0x2074
  143 #define CAS_TX_RING_PTR_LO4     0x2078
  144 #define CAS_TX_RING_PTR_HI4     0x207c
  145 #define CAS_TX_MAXBURST1        0x2080
  146 #define CAS_TX_MAXBURST2        0x2084
  147 #define CAS_TX_MAXBURST3        0x2088
  148 #define CAS_TX_MAXBURST4        0x208c
  150 #define CAS_TX_KICK             CAS_TX_KICK3
  151 #define CAS_TX_RING_PTR_LO      CAS_TX_RING_PTR_LO3
  152 #define CAS_TX_RING_PTR_HI      CAS_TX_RING_PTR_HI3
  154 #define CAS_TX_FIFO_ADDRESS     0x2104
  155 #define CAS_TX_FIFO_TAG         0x2108
  156 #define CAS_TX_FIFO_DATA_LO     0x210c
  157 #define CAS_TX_FIFO_DATA_HI_T1  0x2110
  158 #define CAS_TX_FIFO_DATA_HI_T0  0x2114
  159 #define CAS_TX_FIFO_SIZE        0x2118
  160 #define CAS_TX_DEBUG            0x3028
  162 /* CAS_TX_CONFIG register bits. */
  163 #define CAS_TX_CONFIG_TXDMA_EN  0x00000001      /* TX DMA enable */
  164 #define CAS_TX_CONFIG_TXRING_SZ 0x0000003c      /* TX ring size */
  165 #define CAS_TX_CONFIG_PACED     0x00100000      /* TX_all_int modifier */
  167 #define CAS_RING_SZ_32          0       /* 32 descriptors */
  168 #define CAS_RING_SZ_64          1
  169 #define CAS_RING_SZ_128         2
  170 #define CAS_RING_SZ_256         3
  171 #define CAS_RING_SZ_512         4
  172 #define CAS_RING_SZ_1024        5
  173 #define CAS_RING_SZ_2048        6
  174 #define CAS_RING_SZ_4096        7
  175 #define CAS_RING_SZ_8192        8
  177 /* CAS_TX_COMPLETION register bits */
  178 #define CAS_TX_COMPLETION_MASK  0x00001fff      /* # of last descriptor */
  180 /* RX DMA registers */
  181 #define CAS_RX_CONFIG           0x4000
  182 #define CAS_RX_PAGE_SIZE        0x4004
  183 #define CAS_RX_FIFO_WR_PTR      0x4008          /* FIFO write pointer */
  184 #define CAS_RX_FIFO_RD_PTR      0x400c          /* FIFO read pointer */
  185 #define CAS_RX_IPPFIFO_WR_PTR   0x4010          /* IPP FIFO write pointer */
  186 #define CAS_RX_IPPFIFO_RD_PTR   0x4014          /* IPP FIFO read pointer */
  187 #define CAS_RX_IPPFIFO_SDWR_PTR 0x4018          /* FIFO shadow write pointer */
  188 #define CAS_RX_DEBUG            0x401c          /* Debug reg */
  189 #define CAS_RX_PAUSE_THRESH     0x4020
  190 #define CAS_RX_KICK             0x4024          /* Write last valid desc + 1 */
  191 #define CAS_RX_DRING_PTR_LO     0x4028
  192 #define CAS_RX_DRING_PTR_HI     0x402c
  193 #define CAS_RX_CRING_PTR_LO     0x4030
  194 #define CAS_RX_CRING_PTR_HI     0x4034
  195 #define CAS_RX_COMPLETION       0x4038          /* First pending desc */
  196 #define CAS_RX_COMP_HEAD        0x403c
  197 #define CAS_RX_COMP_TAIL        0x4040
  198 #define CAS_RX_BLANKING         0x4044          /* Interrupt blanking reg */
  199 #define CAS_RX_RED              0x404c          /* Random Early Detection */
  201 #define CAS_RX_IPP_PKT_CNT      0x4054          /* IPP packet counter */
  203 #define CAS_RX_FIFO_ADDRESS     0x4080
  204 #define CAS_RX_FIFO_TAG         0x4084
  205 #define CAS_RX_FIFO_DATA_LO     0x4088
  206 #define CAS_RX_FIFO_DATA_HI_T0  0x408c
  207 #define CAS_RX_FIFO_DATA_HI_T1  0x4090
  209 /* CAS_RX_CONFIG register bits. */
  210 #define CAS_RX_CONFIG_RXDMA_EN  0x00000001      /* RX DMA enable */
  211 #define CAS_RX_CONFIG_RXDRNG_SZ 0x0000001e      /* RX descriptor ring size */
  212 #define CAS_RX_CONFIG_RXCRNG_SZ 0x000001e0      /* RX completion ring size */
  213 #define CAS_RX_CONFIG_BATCH_DIS 0x00000200      /* desc batching disable */
  214 #define CAS_RX_CONFIG_FBOFF     0x00001c00      /* first byte offset */
  216 #define CAS_RX_CONFIG_RXDRNG_SZ_SHIFT   1
  217 #define CAS_RX_CONFIG_RXCRNG_SZ_SHIFT   5
  218 #define CAS_RX_CONFIG_FBOFF_SHFT        10
  220 /* CAS_RX_PAGE_SIZE register bits. */
  221 #define CAS_RX_PAGE_SIZE_SZ     0x00000003      /* Page size */
  222 #define CAS_RX_PAGE_SIZE_COUNT  0x00007800      /* MTU buffers per page */
  223 #define CAS_RX_PAGE_SIZE_STRIDE 0x18000000      /* MTU buffer seperation */
  224 #define CAS_RX_PAGE_SIZE_FBOFF  0xc0000000      /* Firts byte offset */
  226 #define CAS_RX_PAGE_SIZE_COUNT_SHIFT    11
  227 #define CAS_RX_PAGE_SIZE_STRIDE_SHIFT   27
  228 #define CAS_RX_PAGE_SIZE_FBOFF_SHIFT    30
  230 /* CAS_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
  231 #define CAS_RX_PTH_XOFF_THRESH  0x000001ff
  232 #define CAS_RX_PTH_XON_THRESH   0x07fc0000
  234 /* CAS_RX_BLANKING register bits */
  235 #define CAS_RX_BLANKING_PACKETS 0x000001ff      /* Delay intr for x packets */
  236 #define CAS_RX_BLANKING_TIME    0x03fc0000      /* Delay intr for x ticks */
  237 /* One tick is 1048 PCI clocks, or 16us at 66MHz */
  239 /* CAS_MAC registers */
  240 #define CAS_MAC_TXRESET         0x6000          /* Store 1, cleared when done */
  241 #define CAS_MAC_RXRESET         0x6004          /* ditto */
  242 #define CAS_MAC_SEND_PAUSE_CMD  0x6008
  243 #define CAS_MAC_TX_STATUS       0x6010
  244 #define CAS_MAC_RX_STATUS       0x6014
  245 #define CAS_MAC_CONTROL_STATUS  0x6018          /* MAC control status reg */
  246 #define CAS_MAC_TX_MASK         0x6020          /* TX MAC mask register */
  247 #define CAS_MAC_RX_MASK         0x6024
  248 #define CAS_MAC_CONTROL_MASK    0x6028
  249 #define CAS_MAC_TX_CONFIG       0x6030
  250 #define CAS_MAC_RX_CONFIG       0x6034
  251 #define CAS_MAC_CONTROL_CONFIG  0x6038
  252 #define CAS_MAC_XIF_CONFIG      0x603c
  253 #define CAS_MAC_IPG0            0x6040          /* inter packet gap 0 */
  254 #define CAS_MAC_IPG1            0x6044          /* inter packet gap 1 */
  255 #define CAS_MAC_IPG2            0x6048          /* inter packet gap 2 */
  256 #define CAS_MAC_SLOT_TIME       0x604c          /* slot time, bits 0-7 */
  257 #define CAS_MAC_MAC_MIN_FRAME   0x6050
  258 #define CAS_MAC_MAC_MAX_FRAME   0x6054
  259 #define CAS_MAC_PREAMBLE_LEN    0x6058
  260 #define CAS_MAC_JAM_SIZE        0x605c
  261 #define CAS_MAC_ATTEMPT_LIMIT   0x6060
  262 #define CAS_MAC_CONTROL_TYPE    0x6064
  264 #define CAS_MAC_ADDR0           0x6080          /* Normal MAC address 0 */
  265 #define CAS_MAC_ADDR1           0x6084
  266 #define CAS_MAC_ADDR2           0x6088
  267 #define CAS_MAC_ADDR3           0x608c          /* Alternate MAC address 0 */
  268 #define CAS_MAC_ADDR4           0x6090
  269 #define CAS_MAC_ADDR5           0x6094
  270 #define CAS_MAC_ADDR42          0x6128          /* Control MAC address 0 */
  271 #define CAS_MAC_ADDR43          0x612c
  272 #define CAS_MAC_ADDR44          0x6130
  274 #define CAS_MAC_ADDR_FILTER0    0x614c
  275 #define CAS_MAC_ADDR_FILTER1    0x6150
  276 #define CAS_MAC_ADDR_FILTER2    0x6154
  277 #define CAS_MAC_ADR_FLT_MASK1_2 0x6158          /* Address filter mask 1,2 */
  278 #define CAS_MAC_ADR_FLT_MASK0   0x615c          /* Address filter mask 0 reg */
  280 #define CAS_MAC_HASH0           0x6160          /* Hash table 0 */
  281 #define CAS_MAC_HASH1           0x6164
  282 #define CAS_MAC_HASH2           0x6168
  283 #define CAS_MAC_HASH3           0x616c
  284 #define CAS_MAC_HASH4           0x6170
  285 #define CAS_MAC_HASH5           0x6174
  286 #define CAS_MAC_HASH6           0x6178
  287 #define CAS_MAC_HASH7           0x617c
  288 #define CAS_MAC_HASH8           0x6180
  289 #define CAS_MAC_HASH9           0x6184
  290 #define CAS_MAC_HASH10          0x6188
  291 #define CAS_MAC_HASH11          0x618c
  292 #define CAS_MAC_HASH12          0x6190
  293 #define CAS_MAC_HASH13          0x6194
  294 #define CAS_MAC_HASH14          0x6198
  295 #define CAS_MAC_HASH15          0x619c
  297 #define CAS_MAC_NORM_COLL_CNT   0x61a0          /* Normal collision counter */
  298 #define CAS_MAC_FIRST_COLL_CNT  0x61a4          /* 1st successful collision cntr */
  299 #define CAS_MAC_EXCESS_COLL_CNT 0x61a8          /* Excess collision counter */
  300 #define CAS_MAC_LATE_COLL_CNT   0x61ac          /* Late collision counter */
  301 #define CAS_MAC_DEFER_TMR_CNT   0x61b0          /* defer timer counter */
  302 #define CAS_MAC_PEAK_ATTEMPTS   0x61b4
  303 #define CAS_MAC_RX_FRAME_COUNT  0x61b8
  304 #define CAS_MAC_RX_LEN_ERR_CNT  0x61bc
  305 #define CAS_MAC_RX_ALIGN_ERR    0x61c0
  306 #define CAS_MAC_RX_CRC_ERR_CNT  0x61c4
  307 #define CAS_MAC_RX_CODE_VIOL    0x61c8
  308 #define CAS_MAC_RANDOM_SEED     0x61cc
  309 #define CAS_MAC_MAC_STATE       0x61d0          /* MAC sstate machine reg */
  311 /* CAS_MAC_SEND_PAUSE_CMD register bits */
  312 #define CAS_MAC_PAUSE_CMD_TIME  0x0000ffff
  313 #define CAS_MAC_PAUSE_CMD_SEND  0x00010000
  315 /* CAS_MAC_TX_STATUS and _MASK register bits */
  316 #define CAS_MAC_TX_XMIT_DONE    0x00000001
  317 #define CAS_MAC_TX_UNDERRUN     0x00000002
  318 #define CAS_MAC_TX_PKT_TOO_LONG 0x00000004
  319 #define CAS_MAC_TX_NCC_EXP      0x00000008      /* Normal collision cnt exp */
  320 #define CAS_MAC_TX_ECC_EXP      0x00000010
  321 #define CAS_MAC_TX_LCC_EXP      0x00000020
  322 #define CAS_MAC_TX_FCC_EXP      0x00000040
  323 #define CAS_MAC_TX_DEFER_EXP    0x00000080
  324 #define CAS_MAC_TX_PEAK_EXP     0x00000100
  326 /* CAS_MAC_RX_STATUS and _MASK register bits */
  327 #define CAS_MAC_RX_DONE         0x00000001
  328 #define CAS_MAC_RX_OVERFLOW     0x00000002
  329 #define CAS_MAC_RX_FRAME_CNT    0x00000004
  330 #define CAS_MAC_RX_ALIGN_EXP    0x00000008
  331 #define CAS_MAC_RX_CRC_EXP      0x00000010
  332 #define CAS_MAC_RX_LEN_EXP      0x00000020
  333 #define CAS_MAC_RX_CVI_EXP      0x00000040      /* Code violation */
  335 /* CAS_MAC_CONTROL_STATUS and CAS_MAC_CONTROL_MASK register bits */
  336 #define CAS_MAC_PAUSED          0x00000001      /* Pause received */
  337 #define CAS_MAC_PAUSE           0x00000002      /* enter pause state */
  338 #define CAS_MAC_RESUME          0x00000004      /* exit pause state */
  339 #define CAS_MAC_PAUSE_TIME      0xffff0000
  341 /* CAS_MAC_XIF_CONFIG register bits */
  342 #define CAS_MAC_XIF_TX_MII_ENA  0x00000001      /* Enable XIF output drivers */
  343 #define CAS_MAC_XIF_MII_LOOPBK  0x00000002      /* Enable MII loopback mode */
  344 #define CAS_MAC_XIF_ECHO_DISABL 0x00000004      /* Disable echo */
  345 #define CAS_MAC_XIF_GMII_MODE   0x00000008      /* Select GMII/MII mode */
  346 #define CAS_MAC_XIF_MII_BUF_ENA 0x00000010      /* Enable MII recv buffers */
  347 #define CAS_MAC_XIF_LINK_LED    0x00000020      /* force link LED active */
  348 #define CAS_MAC_XIF_FDPLX_LED   0x00000040      /* force FDPLX LED active */
  350 /* CAS_MAC_SLOT_TIME register bits */
  351 #define CAS_MAC_SLOT_INT        0x40
  352 #define CAS_MAC_SLOT_EXT        0x200           /* external phy */
  354 /* CAS_MAC_TX_CONFIG register bits */
  355 #define CAS_MAC_TX_ENABLE       0x00000001      /* TX enable */
  356 #define CAS_MAC_TX_IGN_CARRIER  0x00000002      /* Ignore carrier sense */
  357 #define CAS_MAC_TX_IGN_COLLIS   0x00000004      /* ignore collisions */
  358 #define CAS_MAC_TX_ENA_IPG0     0x00000008      /* extend Rx-to-TX IPG */
  359 #define CAS_MAC_TX_NGU          0x00000010      /* Never give up */
  360 #define CAS_MAC_TX_NGU_LIMIT    0x00000020      /* Never give up limit */
  361 #define CAS_MAC_TX_NO_BACKOFF   0x00000040
  362 #define CAS_MAC_TX_SLOWDOWN     0x00000080
  363 #define CAS_MAC_TX_NO_FCS       0x00000100      /* no FCS will be generated */
  364 #define CAS_MAC_TX_CARR_EXTEND  0x00000200      /* Ena TX Carrier Extension */
  365 /* Carrier Extension is required for half duplex Gbps operation */
  367 /* CAS_MAC_RX_CONFIG register bits */
  368 #define CAS_MAC_RX_ENABLE       0x00000001      /* RX enable */
  369 #define CAS_MAC_RX_STRIP_PAD    0x00000002      /* strip pad bytes */
  370 #define CAS_MAC_RX_STRIP_CRC    0x00000004
  371 #define CAS_MAC_RX_PROMISCUOUS  0x00000008      /* promiscuous mode */
  372 #define CAS_MAC_RX_PROMISC_GRP  0x00000010      /* promiscuous group mode */
  373 #define CAS_MAC_RX_HASH_FILTER  0x00000020      /* enable hash filter */
  374 #define CAS_MAC_RX_ADDR_FILTER  0x00000040      /* enable address filter */
  375 #define CAS_MAC_RX_ERRCHK_DIS   0x00000080      /* disable error checking */
  376 #define CAS_MAC_RX_CARR_EXTEND  0x00000100      /* Ena RX Carrier Extension */
  377 /*
  378  * Carrier Extension enables reception of packet bursts generated by
  379  * senders with carrier extension enabled.
  380  */
  382 /* CAS_MAC_CONTROL_CONFIG bits */
  383 #define CAS_MAC_CC_TX_PAUSE     0x00000001      /* send pause enabled */
  384 #define CAS_MAC_CC_RX_PAUSE     0x00000002      /* receive pause enabled */
  385 #define CAS_MAC_CC_PASS_PAUSE   0x00000004      /* pass pause up */
  387 /* Cassini MIF registers */
  388 /* Bit bang registers use low bit only */
  389 #define CAS_MIF_BB_CLOCK        0x6200          /* bit bang clock */
  390 #define CAS_MIF_BB_DATA         0x6204          /* bit bang data */
  391 #define CAS_MIF_BB_OUTPUT_ENAB  0x6208
  392 #define CAS_MIF_FRAME           0x620c          /* MIF frame - ctl and data */
  393 #define CAS_MIF_CONFIG          0x6210
  394 #define CAS_MIF_INTERRUPT_MASK  0x6214
  395 #define CAS_MIF_BASIC_STATUS    0x6218
  396 #define CAS_MIF_STATE_MACHINE   0x621c
  398 /* CAS_MIF_FRAME bits */
  399 #define CAS_MIF_FRAME_DATA      0x0000ffff
  400 #define CAS_MIF_FRAME_TA0       0x00010000      /* TA bit, 1 for completion */
  401 #define CAS_MIF_FRAME_TA1       0x00020000      /* TA bits */
  402 #define CAS_MIF_FRAME_REG_ADDR  0x007c0000
  403 #define CAS_MIF_FRAME_PHY_ADDR  0x0f800000      /* phy address, should be 0 */
  404 #define CAS_MIF_FRAME_OP        0x30000000      /* operation - write/read */
  405 #define CAS_MIF_FRAME_START     0xc0000000      /* START bits */
  407 #define CAS_MIF_FRAME_READ      0x60020000
  408 #define CAS_MIF_FRAME_WRITE     0x50020000
  410 #define CAS_MIF_REG_SHIFT       18
  411 #define CAS_MIF_PHY_SHIFT       23
  413 /* CAS_MIF_CONFIG register bits */
  414 #define CAS_MIF_CONFIG_PHY_SEL  0x00000001      /* PHY select, 0=MDIO0 */
  415 #define CAS_MIF_CONFIG_POLL_ENA 0x00000002      /* poll enable */
  416 #define CAS_MIF_CONFIG_BB_ENA   0x00000004      /* bit bang enable */
  417 #define CAS_MIF_CONFIG_REG_ADR  0x000000f8      /* poll register address */
  418 #define CAS_MIF_CONFIG_MDI0     0x00000100      /* MDIO_0 Data/MDIO_0 atached */
  419 #define CAS_MIF_CONFIG_MDI1     0x00000200      /* MDIO_1 Data/MDIO_1 atached */
  420 #define CAS_MIF_CONFIG_PHY_ADR  0x00007c00      /* poll PHY address */
  421 /* MDI0 is onboard transceiver MID1 is external, PHYAD for both is 0 */
  423 /* CAS_MIF_BASIC_STATUS and CAS_MIF_INTERRUPT_MASK bits */
  424 #define CAS_MIF_STATUS          0x0000ffff
  425 #define CAS_MIF_BASIC           0xffff0000
  426 /*
  427  * The Basic part is the last value read in the POLL field of the config
  428  * register.
  429  *
  430  * The status part indicates the bits that have changed.
  431  */
  433 /* Cassini PCS/Serial link registers */
  434 #define CAS_MII_CONTROL         0x9000
  435 #define CAS_MII_STATUS          0x9004
  436 #define CAS_MII_ANAR            0x9008          /* MII advertisement reg */
  437 #define CAS_MII_ANLPAR          0x900c          /* Link Partner Ability Reg */
  438 #define CAS_MII_CONFIG          0x9010
  439 #define CAS_MII_STATE_MACHINE   0x9014
  440 #define CAS_MII_INTERRUP_STATUS 0x9018          /* PCS interrupt state */
  441 #define CAS_MII_DATAPATH_MODE   0x9050
  442 #define CAS_MII_SLINK_CONTROL   0x9054          /* Serial link control */
  443 #define CAS_MII_OUTPUT_SELECT   0x9058
  444 #define CAS_MII_SLINK_STATUS    0x905c          /* serial link status */
  446 /* CAS_MII_CONTROL bits */
  447 #define CAS_MII_CONTROL_RESET   0x00008000
  448 #define CAS_MII_CONTROL_LOOPBK  0x00004000      /* 10-bit i/f loopback */
  449 #define CAS_MII_CONTROL_1000M   0x00002000      /* speed select, always 0 */
  450 #define CAS_MII_CONTROL_AUTONEG 0x00001000      /* auto negotiation enabled */
  451 #define CAS_MII_CONTROL_POWERDN 0x00000800
  452 #define CAS_MII_CONTROL_ISOLATE 0x00000400      /* isolate phy from mii */
  453 #define CAS_MII_CONTROL_RAN     0x00000200      /* restart auto negotiation */
  454 #define CAS_MII_CONTROL_FDUPLEX 0x00000100      /* full duplex, always 0 */
  455 #define CAS_MII_CONTROL_COL_TST 0x00000080      /* collision test */
  457 /* CAS_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
  458 #define CAS_MII_STATUS_GB_FDX   0x00000400      /* can perform GBit FDX */
  459 #define CAS_MII_STATUS_GB_HDX   0x00000200      /* can perform GBit HDX */
  460 #define CAS_MII_STATUS_UNK      0x00000100
  461 #define CAS_MII_STATUS_ANEG_CPT 0x00000020      /* auto negotiate compete */
  462 #define CAS_MII_STATUS_REM_FLT  0x00000010      /* remote fault detected */
  463 #define CAS_MII_STATUS_ACFG     0x00000008      /* can auto negotiate */
  464 #define CAS_MII_STATUS_LINK_STS 0x00000004      /* link status */
  465 #define CAS_MII_STATUS_JABBER   0x00000002      /* jabber condition detected */
  466 #define CAS_MII_STATUS_EXTCAP   0x00000001      /* extended register capability */
  468 /* CAS_MII_ANAR and CAS_MII_ANLPAR reg bits */
  469 #define CAS_MII_ANEG_NP         0x00008000      /* next page bit */
  470 #define CAS_MII_ANEG_ACK        0x00004000      /* ack reception of */
  471                                                 /* Link Partner Capability */
  472 #define CAS_MII_ANEG_RF         0x00003000      /* advertise remote fault cap */
  473 #define CAS_MII_ANEG_ASYM_PAUSE 0x00000100      /* asymmetric pause */
  474 #define CAS_MII_ANEG_SYM_PAUSE  0x00000080      /* symmetric pause */
  475 #define CAS_MII_ANEG_HLF_DUPLX  0x00000040
  476 #define CAS_MII_ANEG_FUL_DUPLX  0x00000020
  478 /* CAS_MII_CONFIG reg */
  479 #define CAS_MII_CONFIG_TIMER    0x0000000e      /* link monitor timer values */
  480 #define CAS_MII_CONFIG_ANTO     0x00000020      /* 10ms ANEG timer override */
  481 #define CAS_MII_CONFIG_JS       0x00000018      /* Jitter Study, 0 normal
  482                                                  * 1 high freq, 2 low freq */
  483 #define CAS_MII_CONFIG_SDL      0x00000004      /* Signal Detect active low */
  484 #define CAS_MII_CONFIG_SDO      0x00000002      /* Signal Detect Override */
  485 #define CAS_MII_CONFIG_ENABLE   0x00000001      /* Enable PCS */
  487 /*
  488  * CAS_MII_STATE_MACHINE
  489  * XXX These are best guesses from observed behavior.
  490  */
  491 #define CAS_MII_FSM_STOP        0x00000000      /* stopped */
  492 #define CAS_MII_FSM_RUN         0x00000001      /* running */
  493 #define CAS_MII_FSM_UNKWN       0x00000100      /* unknown */
  494 #define CAS_MII_FSM_DONE        0x00000101      /* complete */
  496 /*
  497  * CAS_MII_INTERRUP_STATUS reg
  498  * No mask register; mask with the global interrupt mask register.
  499  */
  500 #define CAS_MII_INTERRUP_LINK   0x00000002      /* PCS link status change */
  502 /* CAS_MII_DATAPATH_MODE reg */
  503 #define CAS_MII_DATAPATH_SERIAL 0x00000001      /* Serial link */
  504 #define CAS_MII_DATAPATH_SERDES 0x00000002      /* Use PCS via 10bit interfac */
  505 #define CAS_MII_DATAPATH_MII    0x00000004      /* Use {G}MII, not PCS */
  506 #define CAS_MII_DATAPATH_MIIOUT 0x00000008      /* enable serial output on GMII */
  508 /* CAS_MII_SLINK_CONTROL reg */
  509 #define CAS_MII_SLINK_LOOPBACK  0x00000001      /* enable loopback at sl, logic
  510                                                  * reversed for SERDES */
  511 #define CAS_MII_SLINK_EN_SYNC_D 0x00000002      /* enable sync detection */
  512 #define CAS_MII_SLINK_LOCK_REF  0x00000004      /* lock reference clock */
  513 #define CAS_MII_SLINK_EMPHASIS  0x00000008      /* enable emphasis */
  514 #define CAS_MII_SLINK_SELFTEST  0x000001c0
  515 #define CAS_MII_SLINK_POWER_OFF 0x00000200      /* Power down serial link */
  517 /* CAS_MII_SLINK_STATUS reg */
  518 #define CAS_MII_SLINK_TEST      0x00000000      /* undergoing test */
  519 #define CAS_MII_SLINK_LOCKED    0x00000001      /* waiting 500us lockrefn */
  520 #define CAS_MII_SLINK_COMMA     0x00000002      /* waiting for comma detect */
  521 #define CAS_MII_SLINK_SYNC      0x00000003      /* recv data synchronized */
  523 /* Wired PHY addresses */
  524 #define CAS_PHYAD_INTERNAL      1
  525 #define CAS_PHYAD_EXTERNAL      0
  527 /*
  528  * Cassini ring structures.
  529  */
  531 /* Descriptor rings */
  532 struct cas_desc {
uint64_t        cd_flags;
uint64_t        cd_addr;
  535 };
  537 /* Transmit flags */
  538 #define CAS_TD_BUFSIZE          0x0000000000007fffLL
  539 #define CAS_TD_CXSUM_START      0x00000000001f8000LL    /* Cxsum start offset */
  540 #define CAS_TD_CXSUM_STARTSHFT  15
  541 #define CAS_TD_CXSUM_STUFF      0x000000001fe00000LL    /* Cxsum stuff offset */
  542 #define CAS_TD_CXSUM_STUFFSHFT  21
  543 #define CAS_TD_CXSUM_ENABLE     0x0000000020000000LL    /* Cxsum generation enable */
  544 #define CAS_TD_END_OF_PACKET    0x0000000040000000LL
  545 #define CAS_TD_START_OF_PACKET  0x0000000080000000LL
  546 #define CAS_TD_INTERRUPT_ME     0x0000000100000000LL    /* Interrupt me now */
  547 #define CAS_TD_NO_CRC           0x0000000200000000LL    /* do not insert crc */
  548 /*
  549  * Only need to set CAS_TD_CXSUM_ENABLE, CAS_TD_CXSUM_STUFF,
  550  * CAS_TD_CXSUM_START, and CAS_TD_INTERRUPT_ME in 1st descriptor of a group.
  551  */
  553 /* Completion ring */
  554 struct cas_comp {
u_int64_t       cc_word[4];
  556 };
  558 #define CAS_RC0_TYPE            0xc000000000000000ULL
  559 #define CAS_RC0_RELEASE_HDR     0x2000000000000000ULL
  560 #define CAS_RC0_RELEASE_DATA    0x1000000000000000ULL
  561 #define CAS_RC0_SPLIT           0x0400000000000000ULL
  562 #define CAS_RC0_SKIP_MASK       0x0180000000000000ULL
  563 #define CAS_RC0_SKIP_SHIFT      55
  564 #define CAS_RC0_DATA_IDX_MASK   0x007ffe0000000000ULL
  565 #define CAS_RC0_DATA_IDX_SHIFT  41
  566 #define CAS_RC0_DATA_OFF_MASK   0x000001fff8000000ULL
  567 #define CAS_RC0_DATA_OFF_SHIFT  27
  568 #define CAS_RC0_DATA_LEN_MASK   0x0000000007ffe000ULL
  569 #define CAS_RC0_DATA_LEN_SHIFT  13
  571 #define CAS_RC0_SKIP(w) \
  572         (((w) & CAS_RC0_SKIP_MASK) >> CAS_RC0_SKIP_SHIFT)
  573 #define CAS_RC0_DATA_IDX(w) \
  574         (((w) & CAS_RC0_DATA_IDX_MASK) >> CAS_RC0_DATA_IDX_SHIFT)
  575 #define CAS_RC0_DATA_OFF(w) \
  576         (((w) & CAS_RC0_DATA_OFF_MASK) >> CAS_RC0_DATA_OFF_SHIFT)
  577 #define CAS_RC0_DATA_LEN(w) \
  578         (((w) & CAS_RC0_DATA_LEN_MASK) >> CAS_RC0_DATA_LEN_SHIFT)
  580 #define CAS_RC1_HDR_IDX_MASK    0xfffc000000000000ULL
  581 #define CAS_RC1_HDR_IDX_SHIFT   50
  582 #define CAS_RC1_HDR_OFF_MASK    0x0003f00000000000ULL
  583 #define CAS_RC1_HDR_OFF_SHIFT   44
  584 #define CAS_RC1_HDR_LEN_MASK    0x00000ff800000000ULL
  585 #define CAS_RC1_HDR_LEN_SHIFT   35
  587 #define CAS_RC1_HDR_IDX(w) \
  588         (((w) & CAS_RC1_HDR_IDX_MASK) >> CAS_RC1_HDR_IDX_SHIFT)
  589 #define CAS_RC1_HDR_OFF(w) \
  590         (((w) & CAS_RC1_HDR_OFF_MASK) >> CAS_RC1_HDR_OFF_SHIFT)
  591 #define CAS_RC1_HDR_LEN(w) \
  592         (((w) & CAS_RC1_HDR_LEN_MASK) >> CAS_RC1_HDR_LEN_SHIFT)
  594 #define CAS_RC3_OWN             0x0000080000000000ULL /* Owned by hardware */
  596 #endif /* _IF_CASREG_H */