1 /* $OpenBSD: sqphyreg.h,v 1.3 2003/10/22 09:39:29 jmc Exp $ */
2 /* $NetBSD: sqphyreg.h,v 1.1 1998/11/03 23:51:29 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 #ifndef _DEV_MII_SQPHYREG_H_
42 #define _DEV_MII_SQPHYREG_H_
43
44 /*
45 * Seeq 80220 Register definitions.
46 * Further documentation can be found at:
47 * http://www.seeq.com/80220.html
48 */
49
50 #define MII_SQPHY_CONFIG1 0x10 /* Configuration 1 Register */
51 #define CONFIG1_LNK_DIS 0x8000 /* Link Detect Disable */
52 #define CONFIG1_XMT_DIS 0x4000 /* TP Transmitter Disable */
53 #define CONFIG1_XMT_PDN 0x2000 /* TP Transmitter Powerdown */
54 #define CONFIG1_TXEN_CRS 0x1000 /* TX_EN to CRS Loopback Disable */
55 #define CONFIG1_BYP_ENC 0x0800 /* Bypass Encoder */
56 #define CONFIG1_BYP_SCR 0x0400 /* Bypass Scrambler */
57 #define CONFIG1_UNSCR_DIS 0x0200 /* Unscr. Idle Reception Disable */
58 #define CONFIG1_EQLZR 0x0100 /* Rx Equalizer Disable */
59 #define CONFIG1_CABLE 0x0080 /* Cable: 1 = STP, 0 = UTP */
60 #define CONFIG1_RLVL0 0x0040 /* Receive Level Adjust */
61 #define CONFIG1_TLVL3 0x0020 /* Transmit output level adjust */
62 #define CONFIG1_TLVL2 0x0010
63 #define CONFIG1_TLVL1 0x0008
64 #define CONFIG1_TLVL0 0x0004
65 #define CONFIG1_TRF1 0x0002 /* Transmitter Rise/Fall Adjust */
66 #define CONFIG1_TRF0 0x0001
67
68 #define MII_SQPHY_CONFIG2 0x11 /* Configuration 2 Register */
69 #define CONFIG2_PLED3_1 0x8000 /* PLED3 configuration */
70 #define CONFIG2_PLED3_0 0x4000
71 /* 1 1 LINK100 (default) */
72 /* 1 0 Blink */
73 /* 0 1 On */
74 /* 0 0 Off */
75 #define CONFIG2_PLED2_1 0x2000 /* PLED2 configuration */
76 #define CONFIG2_PLED2_0 0x1000
77 /* 1 1 Activity (default) */
78 /* 1 0 Blink */
79 /* 0 1 On */
80 /* 0 0 Off */
81 #define CONFIG2_PLED1_1 0x0800 /* PLED1 configuration */
82 #define CONFIG2_PLED1_0 0x0400
83 /* 1 1 Full duplex (default) */
84 /* 1 0 Blink */
85 /* 0 1 On */
86 /* 0 0 Off */
87 #define CONFIG2_PLED0_1 0x0200 /* PLED0 configuration */
88 #define CONFIG2_PLED0_0 0x0100
89 /* 1 1 LINK10 (default) */
90 /* 1 0 Blink */
91 /* 0 1 On */
92 /* 0 0 Off */
93 #define CONFIG2_LED_DEF1 0x0080 /* LED Normal Function Select */
94 #define CONFIG2_LED_DEF0 0x0040
95 #define CONFIG2_APOL_DIS 0x0020 /* Auto Polarity Correct Disable */
96 #define CONFIG2_JAB_DIS 0x0010 /* Jabber Disable */
97 #define CONFIG2_MREG 0x0008 /* Multiple Register Access Enable */
98 #define CONFIG2_INT_MDIO 0x0004 /* MDIO Interrupt when idle */
99 #define CONFIG2_RJ_CFG 0x0002 /* R/J Configuration Select */
100
101 #define MII_SQPHY_STATUS 0x12 /* Status Output Register */
102 #define STATUS_INT 0x8000 /* Interrupt Detect */
103 #define STATUS_LNK_FAIL 0x4000 /* Link Fail */
104 #define STATUS_LOSS_SYNC 0x2000 /* Descrambler lost synchronization */
105 #define STATUS_CWRD 0x1000 /* Codeword Error */
106 #define STATUS_SSD 0x0800 /* Start of Stream Error */
107 #define STATUS_ESD 0x0400 /* End of Stream Error */
108 #define STATUS_RPOL 0x0200 /* Reverse Polarity Detected */
109 #define STATUS_JAB 0x0100 /* Jabber Detected */
110 #define STATUS_SPD_DET 0x0080 /* 100Mbps */
111 #define STATUS_DPLX_DET 0x0040 /* Full Duplex */
112
113 #define MII_SQPHY_MASK 0x13 /* Mask Register */
114 #define MASK_INT 0x8000 /* mask INT */
115 #define MASK_LNK_FAIL 0x4000 /* mask LNK_FAIL */
116 #define MASK_LOSS_SYNC 0x2000 /* mask LOSS_SYNC */
117 #define MASK_CWRD 0x1000 /* mask CWRD */
118 #define MASK_SSD 0x0800 /* mask SSD */
119 #define MASK_ESD 0x0400 /* mask ESD */
120 #define MASK_RPOL 0x0200 /* mask RPOL */
121 #define MASK_JAB 0x0100 /* mask JAB */
122 #define MASK_SPD_DET 0x0080 /* mask SPD_DET */
123 #define MASK_DPLX_DET 0x0040 /* mask DPLX_DET */
124 #define MASK_ANEG_STS1 0x0020 /* mask ANEG_STS1 */
125 #define MASK_ANEG_STS0 0x0010 /* mask ANEG_STS0 */
126
127 #define MII_SQPHY_RESERVED 0x14 /* Reserved Register */
128 /* All bits must be 0 */
129
130 #endif /* _DEV_MII_SQPHYREG_H_ */