1 /* $OpenBSD: inphyreg.h,v 1.4 2003/10/22 09:39:29 jmc Exp $ */
2 /* $NetBSD: inphyreg.h,v 1.1 1998/08/11 00:00:28 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 #ifndef _DEV_MII_INPHYREG_H_
42 #define _DEV_MII_INPHYREG_H_
43
44 /*
45 * Intel 82555, 82562EM, and 82562ET registers.
46 * Note that the 82562 chips are basically 82555 with a few extra registers
47 * and all of the 100baseT4 support removed. Bits in the SCR register do
48 * overlap however.
49 */
50
51 #define MII_INPHY_SCR 0x10 /* Status and Control */
52 #define SCR_FLOWCTL 0x8000 /* PHY Base flow control enabled */
53 #define SCR_CSDC 0x2000 /* Carrier sense disconnect control */
54 #define SCR_TFCD 0x1000 /* Transmit flow control disable */
55 #define SCR_RDSI 0x0800 /* Receive deserializer in-sync */
56 #define SCR_100TXPD 0x0400 /* 100baseTX is powered down */
57 #define SCR_10TPD 0x0200 /* 10baseT is powered down */
58 #define SCR_POLARITY 0x0100 /* reverse 10baseT polarity */
59 #define SCR_T4 0x0004 /* autoneg resulted in 100baseT4 */
60 #define SCR_S100 0x0002 /* autoneg resulted in 100baseTX */
61 #define SCR_FDX 0x0001 /* autoneg resulted in full-duplex */
62 /* 82562E[MT] only */
63 #define SCR_PHYADDR_M 0x007c /* phy address mask */
64 #define SCR_PHYADDR_S 2 /* shift to normalize */
65
66 #define MII_INPHY_SCTRL 0x11 /* Special Control Bit */
67 #define SCTRL_SCRBYPASS 0x8000 /* scrambler bypass */
68 #define SCTRL_4B5BNYPASS 0x4000 /* 4bit to 5bit bypass */
69 #define SCTRL_FTHP 0x2000 /* force transmit H-pattern */
70 #define SCTRL_F34TP 0x1000 /* force 34 transmit patter */
71 #define SCTRL_GOODLINK 0x0800 /* 100baseTX link good */
72 #define SCTRL_TCSD 0x0200 /* transmit carrier sense disable */
73 #define SCTRL_DDPD 0x0100 /* disable dynamic power-down */
74 #define SCTRL_ANEGLOOP 0x0080 /* autonegotiation loopback */
75 #define SCTRL_MDITRISTATE 0x0040 /* MDI Tri-state */
76 #define SCTRL_FILTERBYPASS 0x0020 /* Filter bypass */
77 #define SCTRL_AUTOPOLDIS 0x0010 /* auto-polarity disable */
78 #define SCTRL_SQUELCHDIS 0x0008 /* squlch test disable */
79 #define SCTRL_EXTSQUELCH 0x0004 /* extended sequelch enable */
80 #define SCTRL_LINKINTDIS 0x0002 /* link integrity disable */
81 #define SCTRL_JABBERDIS 0x0001 /* jabber disabled */
82 /* 82562E[MT] only */
83 #define SCTRL_SRE 0x0400 /* symbol error enable */
84 #define SCTRL_FORCEPOL 0x0020 /* force polarity, 0 = normal */
85
86 /* 82562E[MT] only */
87 #define MII_INPHY_PHYADDR 0x12 /* phy address register, 82562 only */
88
89 /* 82562E[MT] only */
90 #define MII_INPHY_100TXFCC 0x13 /* false carrier counter */
91
92 #define MII_INPHY_100TXRDC 0x14 /* 100baseTX Receive Disconnect Cntr */
93
94 #define MII_INPHY_100TXREFC 0x15 /* 100baseTX Receive Error Frame Ctr */
95
96 #define MII_INPHY_RSEC 0x16 /* Receive Symbol Error Counter */
97
98 #define MII_INPHY_100TXRPEOFC 0x17 /* 100baseTX Rcv Premature EOF Ctr */
99
100 #define MII_INPHY_10TREOFC 0x18 /* 10baseT Rcv EOF Ctr */
101
102 #define MII_INPHY_10TTJDC 0x19 /* 10baseT Tx Jabber Detect Ctr */
103
104 #define MII_INPHY_SCTRL2 0x1b /* 82555 Special Control */
105 #define SCTRL2_LEDMASK 0x0007 /* mask of LEDs control: see below */
106
107 #define LEDMASK_ACTLINK 0x0000 /* A = Activity, L = Link */
108 #define LEDMASK_SPDCOLL 0x0001 /* A = Speed, L = Collision */
109 #define LEDMASK_SPDLINK 0x0002 /* A = Speed, L = Link */
110 #define LEDMASK_ACTCOLL 0x0003 /* A = Activity, L = Collision */
111 #define LEDMASK_OFFOFF 0x0004 /* A = off, L = off */
112 #define LEDMASK_OFFON 0x0005 /* A = off, L = on */
113 #define LEDMASK_ONOFF 0x0006 /* A = on, L = off */
114 #define LESMASK_ONON 0x0007 /* A = on, L = on */
115
116 #endif /* _DEV_MII_INPHYREG_H_ */