1 /* $OpenBSD: viasioreg.h,v 1.3 2006/02/24 11:16:17 grange Exp $ */
2 /*
3 * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _DEV_ISA_VIASIOREG_H_
19 #define _DEV_ISA_VIASIOREG_H_
20
21 /*
22 * VIA VT1211 LPC Super I/O register definitions.
23 */
24
25 /*
26 * Obtained from the following datasheet:
27 *
28 * VT1211
29 * Low Pin Count Super I/O And Hardware Monitor
30 * Revision 1.0
31 * January 8, 2002
32 * VIA TECHNOLOGIES, INC.
33 */
34
35 /* ISA bus registers */
36 #define VT1211_INDEX 0x00 /* Configuration Index Register */
37 #define VT1211_DATA 0x01 /* Configuration Data Register */
38
39 #define VT1211_IOSIZE 0x02 /* ISA I/O space size */
40
41 #define VT1211_CONF_EN_MAGIC 0x87 /* enable configuration mode */
42 #define VT1211_CONF_DS_MAGIC 0xaa /* disable configuration mode */
43
44 /* Configuration Space Registers */
45 #define VT1211_LDN 0x07 /* Logical Device Number */
46 #define VT1211_ID 0x20 /* Device ID */
47 #define VT1211_REV 0x21 /* Device Revision */
48 #define VT1211_PDC 0x22 /* Power Down Control */
49 #define VT1211_LPCWSS 0x23 /* LPC Wait State Select */
50 #define VT1211_GPIO1PS 0x24 /* GPIO Port 1 Pin Select */
51 #define VT1211_GPIO2PS 0x25 /* GPIO Port 2 Pin Select */
52 #define VT1211_GPIO7PS 0x26 /* GPIO Port 7 Pin Select */
53 #define VT1211_UART2PS 0x27 /* UART2 Multi Function Pin Select */
54 #define VT1211_MIDIPS 0x28 /* MIDI Multi Function Pin Select */
55 #define VT1211_HWMPS 0x29 /* HWM Multi Function Pin Select */
56 #define VT1211_TMA 0x2e /* Test Mode A */
57 #define VT1211_TMB 0x2f /* Test Mode B */
58
59 #define VT1211_ID_VT1211 0x3c /* VT1211 Device ID */
60
61 /* Logical Device Number (LDN) Assignments */
62 #define VT1211_LDN_FDC 0x00 /* Floppy Disk Controller */
63 #define VT1211_LDN_PP 0x01 /* Parallel Port */
64 #define VT1211_LDN_UART1 0x02 /* Serial Port 1 */
65 #define VT1211_LDN_UART2 0x03 /* Serial Port 2 */
66 #define VT1211_LDN_MIDI 0x06 /* MIDI */
67 #define VT1211_LDN_GMP 0x07 /* Game Port */
68 #define VT1211_LDN_GPIO 0x08 /* GPIO */
69 #define VT1211_LDN_WDG 0x09 /* Watch Dog */
70 #define VT1211_LDN_WUC 0x0a /* Wake-up Control */
71 #define VT1211_LDN_HM 0x0b /* Hardware Monitor */
72 #define VT1211_LDN_VFIR 0x0c /* Very Fast IR */
73 #define VT1211_LDN_ROM 0x0d /* Flash ROM */
74
75 /* Watchdog Timer Control Registers (LDN 9) */
76 #define VT1211_WDG_ACT 0x30 /* Activate */
77 #define VT1211_WDG_ACT_EN (1 << 0) /* enabled */
78 #define VT1211_WDG_ADDR_MSB 0x60 /* Address [15:8] */
79 #define VT1211_WDG_ADDR_LSB 0x61 /* Address [7:0] */
80 #define VT1211_WDG_IRQSEL 0x70 /* IRQ Select */
81 #define VT1211_WDG_CONF 0xf0 /* Configuration */
82
83 /* Hardware Monitor Control Registers (LDN B) */
84 #define VT1211_HM_ACT 0x30 /* Activate */
85 #define VT1211_HM_ACT_EN (1 << 0) /* enabled */
86 #define VT1211_HM_ADDR_MSB 0x60 /* Address [15:8] */
87 #define VT1211_HM_ADDR_LSB 0x61 /* Address [7:0] */
88 #define VT1211_HM_IRQSEL 0x70 /* IRQ Select */
89
90 /* Watchdog Timer I/O Space Registers */
91 #define VT1211_WDG_STAT 0x00 /* Status */
92 #define VT1211_WDG_STAT_ACT (1 << 0) /* timer is active */
93 #define VT1211_WDG_MASK 0x01 /* Mask */
94 #define VT1211_WDG_MASK_COM1 (1 << 1) /* COM1 trigger */
95 #define VT1211_WDG_MASK_COM2 (1 << 2) /* COM2 trigger */
96 #define VT1211_WDG_TIMEOUT 0x02 /* Timeout */
97
98 #define VT1211_WDG_IOSIZE 0x04 /* Watchdog timer I/O space size */
99
100 /* Hardware Monitor I/O Space Registers */
101 #define VT1211_HM_SELD0 0x10 /* SELD[7:0] */
102 #define VT1211_HM_SELD1 0x11 /* SELD[15:8] */
103 #define VT1211_HM_SELD2 0x12 /* SELD[19:16] */
104 #define VT1211_HM_ADATA_MSB 0x13 /* Analog Data D[15:8] */
105 #define VT1211_HM_ADATA_LSB 0x14 /* Analog Data D[7:0] */
106 #define VT1211_HM_DDATA 0x15 /* Digital Data D[7:0] */
107 #define VT1211_HM_CHCNT 0x16 /* Channel Counter */
108 #define VT1211_HM_DVCI 0x17 /* Data Valid & Channel Indications */
109 #define VT1211_HM_SMBUSCTL 0x18 /* SMBus Control */
110 #define VT1211_HM_AFECTL 0x19 /* AFE Control */
111 #define VT1211_HM_AFETCTL 0x1a /* AFE Test Control */
112 #define VT1211_HM_CHSET 0x1b /* Channel Setting */
113 #define VT1211_HM_HTL3 0x1d /* Hot Temp Limit 3 */
114 #define VT1211_HM_HTHL3 0x1e /* Hot Temp Hysteresis Limit 3 */
115 #define VT1211_HM_TEMP1 0x1f /* Temperature Reading 1 */
116 #define VT1211_HM_TEMP3 0x20 /* Temperature Reading 3 */
117 #define VT1211_HM_UCH1 0x21 /* UCH1 */
118 #define VT1211_HM_UCH2 0x22 /* UCH2 */
119 #define VT1211_HM_UCH3 0x23 /* UCH3 */
120 #define VT1211_HM_UCH4 0x24 /* UCH4 */
121 #define VT1211_HM_UCH5 0x25 /* UCH5 */
122 #define VT1211_HM_33V 0x26 /* +3.3V (Internal Vcc ) */
123 #define VT1211_HM_FAN1 0x29 /* FAN1 Reading */
124 #define VT1211_HM_FAN2 0x2a /* FAN2 Reading */
125 #define VT1211_HM_UCH2HL 0x2b /* UCH2 High Limit */
126 #define VT1211_HM_UCH2LL 0x2c /* UCH2 Low Limit */
127 #define VT1211_HM_UCH3HL 0x2d /* UCH3 High Limit */
128 #define VT1211_HM_UCH3LL 0x2e /* UCH3 Low Limit */
129 #define VT1211_HM_UCH4HL 0x2f /* UCH4 High Limit */
130 #define VT1211_HM_UCH4LL 0x30 /* UCH4 Low Limit */
131 #define VT1211_HM_UCH5HL 0x31 /* UCH5 High Limit */
132 #define VT1211_HM_UCH5LL 0x32 /* UCH5 Low Limit */
133 #define VT1211_HM_33VHL 0x33 /* Internal +3.3V High Limit */
134 #define VT1211_HM_33VLL 0x34 /* Internal +3.3V Low Limit */
135 #define VT1211_HM_HTL1 0x39 /* Hot Temp Limit 1 */
136 #define VT1211_HM_HTHL1 0x3a /* Hot Temp Hysteresis Limit 1 */
137 #define VT1211_HM_FAN1CL 0x3b /* FAN1 Fan Count Limit */
138 #define VT1211_HM_FAN2CL 0x3c /* FAN2 Fan Count Limit */
139 #define VT1211_HM_UCH1HL 0x3d /* UCH1 High Limit */
140 #define VT1211_HM_UCH1LL 0x3e /* UCH1 Low Limit */
141 #define VT1211_HM_STEPID 0x3f /* Stepping ID Number */
142 #define VT1211_HM_CONF 0x40 /* Configuration */
143 #define VT1211_HM_CONF_START (1 << 0)
144 #define VT1211_HM_INTST1 0x41 /* Interrupt INT Status 1 */
145 #define VT1211_HM_INTST2 0x42 /* Interrupt INT Status 2 */
146 #define VT1211_HM_INTMASK1 0x43 /* INT Mask 1 */
147 #define VT1211_HM_INTMASK2 0x44 /* INT Mask 2 */
148 #define VT1211_HM_VID 0x45 /* VID */
149 #define VT1211_HM_OVOFCTL 0x46 /* Over Voltage & Over Fan Control */
150 #define VT1211_HM_FSCTL 0x47 /* Fan Speed Control */
151 #define VT1211_HM_FSCTL_DIV1(v) (((v) >> 4) & 0x03)
152 #define VT1211_HM_FSCTL_DIV2(v) (((v) >> 6) & 0x03)
153 #define VT1211_HM_SBA 0x48 /* Serial Bus Address */
154 #define VT1211_HM_VID4 0x49 /* VID 4 */
155 #define VT1211_HM_VID4_UCH1(v) (((v) >> 4) & 0x03)
156 #define VT1211_HM_UCHCONF 0x4a /* Universal Channel Configuration */
157 #define VT1211_HM_UCHCONF_ISTEMP(v, n) (((v) & (1 << ((n) + 1))) != 0)
158 #define VT1211_HM_TCONF1 0x4b /* Temperature Configuration 1 */
159 #define VT1211_HM_TCONF1_TEMP1(v) (((v) >> 6) & 0x03)
160 #define VT1211_HM_TCONF2 0x4c /* Temperature Configuration 2 */
161 #define VT1211_HM_ETR 0x4d /* Extended Temperature Resolution */
162 #define VT1211_HM_ETR_UCH(v, n) (((v) >> (((n) - 2) * 2)) & 0x03)
163 #define VT1211_HM_OTCTL 0x4e /* Over Temperature Control */
164 #define VT1211_HM_PWMCS 0x50 /* PWM Clock Select */
165 #define VT1211_HM_PWMCTL 0x51 /* PWM Control */
166 #define VT1211_HM_PWMFST 0x52 /* PWM Full Speed Temperature Value */
167 #define VT1211_HM_PWMHST 0x53 /* PWM High Speed Temperature Value */
168 #define VT1211_HM_PWMLST 0x54 /* PWM Low Speed Temperature Value */
169 #define VT1211_HM_PWMFOT 0x55 /* PWM Fan Off Temperature Value */
170 #define VT1211_HM_PWMO1HSDC 0x56 /* PWM Output 1 Hi Speed Duty Cycle */
171 #define VT1211_HM_PWMO1LSDC 0x57 /* PWM Output 1 Lo Speed Duty Cycle */
172 #define VT1211_HM_PWMO2HSDC 0x58 /* PWM Output 2 Hi Speed Duty Cycle */
173 #define VT1211_HM_PWMO2LSDC 0x59 /* PWM Output 2 Lo Speed Duty Cycle */
174 #define VT1211_HM_PWMO3HSDC 0x5a /* PWM Output 3 Hi Speed Duty Cycle */
175 #define VT1211_HM_PWMO3LSDC 0x5b /* PWM Output 3 Lo Speed Duty Cycle */
176 #define VT1211_HM_BEEPEN 0x5c /* BEEP Event Enable */
177 #define VT1211_HM_FEBFD 0x5d /* Fan Event BEEP Frequency Divisor */
178 #define VT1211_HM_VEBFD 0x5e /* Volt Event BEEP Frequency Divisor */
179 #define VT1211_HM_TEBFD 0x5f /* Temp Event BEEP Frequency Divisor */
180 #define VT1211_HM_PWM1CDC 0x60 /* PWM1 Current Duty Cycle */
181 #define VT1211_HM_PWM2CDC 0x61 /* PWM2 Current Duty Cycle */
182
183 #define VT1211_HM_IOSIZE 0x80 /* Hardware monitor I/O space size */
184
185 /* PWM clock frequencies */
186 static const int vt1211_hm_clock[] = {
187 90000, 45000, 22500, 11250, 5630, 2800, 1400, 700
188 };
189
190 /* Voltage inputs resistor factors */
191 static const int vt1211_hm_vrfact[] = {
192 5952, 8333, 5952, 4167, 1754, 6296
193 };
194
195 /*
196 * Temperature lookup table for the following conversion formula:
197 *
198 * temp (degC) = (1.0 / (((1.0 / 3435.0) * (log((253.0 - raw / 4.0) /
199 * (raw / 4.0 - 43.0)))) + (1.0 / 298.15))) - 273.15;
200 *
201 */
202 static const struct {
203 int raw; /* raw value */
204 int64_t temp; /* temperature in uK */
205 } vt1211_hm_temptbl[] = {
206 { 176, 203690000LL },
207 { 184, 218020000LL },
208 { 192, 225470000LL },
209 { 200, 230710000LL },
210 { 208, 234830000LL },
211 { 216, 238260000LL },
212 { 224, 241230000LL },
213 { 232, 243850000LL },
214 { 240, 246220000LL },
215 { 248, 248390000LL },
216 { 256, 250390000LL },
217 { 264, 252260000LL },
218 { 272, 254020000LL },
219 { 280, 255680000LL },
220 { 288, 257260000LL },
221 { 296, 258760000LL },
222 { 304, 260210000LL },
223 { 312, 261600000LL },
224 { 320, 262940000LL },
225 { 328, 264240000LL },
226 { 336, 265500000LL },
227 { 344, 266730000LL },
228 { 352, 267930000LL },
229 { 360, 269100000LL },
230 { 368, 270240000LL },
231 { 376, 271360000LL },
232 { 384, 272460000LL },
233 { 392, 273540000LL },
234 { 400, 274610000LL },
235 { 408, 275660000LL },
236 { 416, 276700000LL },
237 { 424, 277720000LL },
238 { 432, 278730000LL },
239 { 440, 279740000LL },
240 { 448, 280730000LL },
241 { 456, 281720000LL },
242 { 464, 282700000LL },
243 { 472, 283670000LL },
244 { 480, 284640000LL },
245 { 488, 285610000LL },
246 { 496, 286570000LL },
247 { 504, 287530000LL },
248 { 512, 288490000LL },
249 { 520, 289450000LL },
250 { 528, 290400000LL },
251 { 536, 291360000LL },
252 { 544, 292320000LL },
253 { 552, 293280000LL },
254 { 560, 294250000LL },
255 { 568, 295210000LL },
256 { 576, 296190000LL },
257 { 584, 297160000LL },
258 { 592, 298150000LL },
259 { 600, 299130000LL },
260 { 608, 300130000LL },
261 { 616, 301140000LL },
262 { 624, 302150000LL },
263 { 632, 303170000LL },
264 { 640, 304210000LL },
265 { 648, 305250000LL },
266 { 656, 306310000LL },
267 { 664, 307380000LL },
268 { 672, 308470000LL },
269 { 680, 309570000LL },
270 { 688, 310690000LL },
271 { 696, 311830000LL },
272 { 704, 312990000LL },
273 { 712, 314170000LL },
274 { 720, 315380000LL },
275 { 728, 316610000LL },
276 { 736, 317860000LL },
277 { 744, 319150000LL },
278 { 752, 320460000LL },
279 { 760, 321810000LL },
280 { 768, 323200000LL },
281 { 776, 324620000LL },
282 { 784, 326090000LL },
283 { 792, 327610000LL },
284 { 800, 329170000LL },
285 { 808, 330790000LL },
286 { 816, 332470000LL },
287 { 824, 334220000LL },
288 { 832, 336040000LL },
289 { 840, 337940000LL },
290 { 848, 339940000LL },
291 { 856, 342030000LL },
292 { 864, 344230000LL },
293 { 872, 346560000LL },
294 { 880, 349030000LL },
295 { 888, 351670000LL },
296 { 896, 354490000LL },
297 { 904, 357530000LL },
298 { 912, 360830000LL },
299 { 920, 364430000LL },
300 { 928, 368410000LL },
301 { 936, 372830000LL },
302 { 944, 377820000LL },
303 { 952, 383530000LL },
304 { 960, 390210000LL },
305 { 968, 398230000LL },
306 { 976, 408200000LL },
307 { 984, 421270000LL },
308 { 992, 439960000LL }
309 };
310
311 /* Hardware monitor sensors */
312 enum {
313 VT1211_HMS_TEMP1 = 0,
314 VT1211_HMS_UCH1,
315 VT1211_HMS_UCH2,
316 VT1211_HMS_UCH3,
317 VT1211_HMS_UCH4,
318 VT1211_HMS_UCH5,
319 VT1211_HMS_33V,
320 VT1211_HMS_FAN1,
321 VT1211_HMS_FAN2,
322 VT1211_HM_NSENSORS /* must be the last */
323 };
324
325 #endif /* !_DEV_ISA_VIASIOREG_H_ */