This source file includes following definitions.
- MFI_STAT_OK
- MFI_STAT_INVALID_CMD
- MFI_STAT_INVALID_DCMD
- MFI_STAT_INVALID_PARAMETER
- MFI_STAT_INVALID_SEQUENCE_NUMBER
- MFI_STAT_ABORT_NOT_POSSIBLE
- MFI_STAT_APP_HOST_CODE_NOT_FOUND
- MFI_STAT_APP_IN_USE
- MFI_STAT_APP_NOT_INITIALIZED
- MFI_STAT_ARRAY_INDEX_INVALID
- MFI_STAT_ARRAY_ROW_NOT_EMPTY
- MFI_STAT_CONFIG_RESOURCE_CONFLICT
- MFI_STAT_DEVICE_NOT_FOUND
- MFI_STAT_DRIVE_TOO_SMALL
- MFI_STAT_FLASH_ALLOC_FAIL
- MFI_STAT_FLASH_BUSY
- MFI_STAT_FLASH_ERROR
- MFI_STAT_FLASH_IMAGE_BAD
- MFI_STAT_FLASH_IMAGE_INCOMPLETE
- MFI_STAT_FLASH_NOT_OPEN
- MFI_STAT_FLASH_NOT_STARTED
- MFI_STAT_FLUSH_FAILED
- MFI_STAT_HOST_CODE_NOT_FOUNT
- MFI_STAT_LD_CC_IN_PROGRESS
- MFI_STAT_LD_INIT_IN_PROGRESS
- MFI_STAT_LD_LBA_OUT_OF_RANGE
- MFI_STAT_LD_MAX_CONFIGURED
- MFI_STAT_LD_NOT_OPTIMAL
- MFI_STAT_LD_RBLD_IN_PROGRESS
- MFI_STAT_LD_RECON_IN_PROGRESS
- MFI_STAT_LD_WRONG_RAID_LEVEL
- MFI_STAT_MAX_SPARES_EXCEEDED
- MFI_STAT_MEMORY_NOT_AVAILABLE
- MFI_STAT_MFC_HW_ERROR
- MFI_STAT_NO_HW_PRESENT
- MFI_STAT_NOT_FOUND
- MFI_STAT_NOT_IN_ENCL
- MFI_STAT_PD_CLEAR_IN_PROGRESS
- MFI_STAT_PD_TYPE_WRONG
- MFI_STAT_PR_DISABLED
- MFI_STAT_ROW_INDEX_INVALID
- MFI_STAT_SAS_CONFIG_INVALID_ACTION
- MFI_STAT_SAS_CONFIG_INVALID_DATA
- MFI_STAT_SAS_CONFIG_INVALID_PAGE
- MFI_STAT_SAS_CONFIG_INVALID_TYPE
- MFI_STAT_SCSI_DONE_WITH_ERROR
- MFI_STAT_SCSI_IO_FAILED
- MFI_STAT_SCSI_RESERVATION_CONFLICT
- MFI_STAT_SHUTDOWN_FAILED
- MFI_STAT_TIME_NOT_SET
- MFI_STAT_WRONG_STATE
- MFI_STAT_LD_OFFLINE
- MFI_STAT_PEER_NOTIFICATION_REJECTED
- MFI_STAT_PEER_NOTIFICATION_FAILED
- MFI_STAT_RESERVATION_IN_PROGRESS
- MFI_STAT_I2C_ERRORS_DETECTED
- MFI_STAT_PCI_ERRORS_DETECTED
- MFI_STAT_INVALID_STATUS
- mfi_status_t
- MFI_EVT_CLASS_DEBUG
- MFI_EVT_CLASS_PROGRESS
- MFI_EVT_CLASS_INFO
- MFI_EVT_CLASS_WARNING
- MFI_EVT_CLASS_CRITICAL
- MFI_EVT_CLASS_FATAL
- MFI_EVT_CLASS_DEAD
- mfi_evt_class_t
- MFI_EVT_LOCALE_LD
- MFI_EVT_LOCALE_PD
- MFI_EVT_LOCALE_ENCL
- MFI_EVT_LOCALE_BBU
- MFI_EVT_LOCALE_SAS
- MFI_EVT_LOCALE_CTRL
- MFI_EVT_LOCALE_CONFIG
- MFI_EVT_LOCALE_CLUSTER
- MFI_EVT_LOCALE_ALL
- mfi_evt_locale_t
- MR_EVT_ARGS_NONE
- MR_EVT_ARGS_CDB_SENSE
- MR_EVT_ARGS_LD
- MR_EVT_ARGS_LD_COUNT
- MR_EVT_ARGS_LD_LBA
- MR_EVT_ARGS_LD_OWNER
- MR_EVT_ARGS_LD_LBA_PD_LBA
- MR_EVT_ARGS_LD_PROG
- MR_EVT_ARGS_LD_STATE
- MR_EVT_ARGS_LD_STRIP
- MR_EVT_ARGS_PD
- MR_EVT_ARGS_PD_ERR
- MR_EVT_ARGS_PD_LBA
- MR_EVT_ARGS_PD_LBA_LD
- MR_EVT_ARGS_PD_PROG
- MR_EVT_ARGS_PD_STATE
- MR_EVT_ARGS_PCI
- MR_EVT_ARGS_RATE
- MR_EVT_ARGS_STR
- MR_EVT_ARGS_TIME
- MR_EVT_ARGS_ECC
- mfi_evt_args
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19 #define MFI_MGMT_VD 0x01
20 #define MFI_MGMT_SD 0x02
21
22
23 #define MFI_FRAME_SIZE 64
24 #define MFI_SENSE_SIZE 128
25 #define MFI_OSTS_INTR_VALID 0x00000002
26 #define MFI_INVALID_CTX 0xffffffff
27 #define MFI_ENABLE_INTR 0x01
28 #define MFI_MAXFER MAXPHYS
29
30
31 #define MFI_IMSG0 0x10
32 #define MFI_IMSG1 0x14
33 #define MFI_OMSG0 0x18
34 #define MFI_OMSG1 0x1c
35 #define MFI_IDB 0x20
36 #define MFI_ISTS 0x24
37 #define MFI_IMSK 0x28
38 #define MFI_ODB 0x2c
39 #define MFI_OSTS 0x30
40 #define MFI_OMSK 0x34
41 #define MFI_IQP 0x40
42 #define MFI_OQP 0x44
43
44
45 #define MFI_STATE_MASK 0xf0000000
46 #define MFI_STATE_UNDEFINED 0x00000000
47 #define MFI_STATE_BB_INIT 0x10000000
48 #define MFI_STATE_FW_INIT 0x40000000
49 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
50 #define MFI_STATE_FW_INIT_2 0x70000000
51 #define MFI_STATE_DEVICE_SCAN 0x80000000
52 #define MFI_STATE_FLUSH_CACHE 0xa0000000
53 #define MFI_STATE_READY 0xb0000000
54 #define MFI_STATE_OPERATIONAL 0xc0000000
55 #define MFI_STATE_FAULT 0xf0000000
56 #define MFI_STATE_MAXSGL_MASK 0x00ff0000
57 #define MFI_STATE_MAXCMD_MASK 0x0000ffff
58
59
60 #define MFI_INIT_ABORT 0x00000000
61 #define MFI_INIT_READY 0x00000002
62 #define MFI_INIT_MFIMODE 0x00000004
63 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
64 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE
65
66
67 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
68 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
69 #define MFI_FRAME_SGL32 0x0000
70 #define MFI_FRAME_SGL64 0x0002
71 #define MFI_FRAME_SENSE32 0x0000
72 #define MFI_FRAME_SENSE64 0x0004
73 #define MFI_FRAME_DIR_NONE 0x0000
74 #define MFI_FRAME_DIR_WRITE 0x0008
75 #define MFI_FRAME_DIR_READ 0x0010
76 #define MFI_FRAME_DIR_BOTH 0x0018
77
78
79 #define MFI_CMD_INIT 0x00
80 #define MFI_CMD_LD_READ 0x01
81 #define MFI_CMD_LD_WRITE 0x02
82 #define MFI_CMD_LD_SCSI_IO 0x03
83 #define MFI_CMD_PD_SCSI_IO 0x04
84 #define MFI_CMD_DCMD 0x05
85 #define MFI_CMD_ABORT 0x06
86 #define MFI_CMD_SMP 0x07
87 #define MFI_CMD_STP 0x08
88
89
90 #define MR_DCMD_CTRL_GET_INFO 0x01010000
91 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
92 #define MR_FLUSH_CTRL_CACHE 0x01
93 #define MR_FLUSH_DISK_CACHE 0x02
94 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
95 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
96 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
97 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
98 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
99 #define MR_DCMD_PD_GET_LIST 0x02010000
100 #define MR_DCMD_PD_GET_INFO 0x02020000
101 #define MD_DCMD_PD_SET_STATE 0x02030100
102 #define MD_DCMD_PD_REBUILD 0x02040100
103 #define MR_DCMD_PD_BLINK 0x02070100
104 #define MR_DCMD_PD_UNBLINK 0x02070200
105 #define MR_DCMD_LD_GET_LIST 0x03010000
106 #define MR_DCMD_LD_GET_INFO 0x03020000
107 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
108 #define MD_DCMD_CONF_GET 0x04010000
109 #define MR_DCMD_CLUSTER 0x08000000
110 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
111 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
112
113 #define MR_DCMD_SPEAKER_GET 0x01030100
114 #define MR_DCMD_SPEAKER_ENABLE 0x01030200
115 #define MR_DCMD_SPEAKER_DISABLE 0x01030300
116 #define MR_DCMD_SPEAKER_SILENCE 0x01030400
117 #define MR_DCMD_SPEAKER_TEST 0x01030500
118
119
120 #define MFI_MBOX_SIZE 12
121
122
123 typedef enum {
124 MFI_STAT_OK = 0x00,
125 MFI_STAT_INVALID_CMD = 0x01,
126 MFI_STAT_INVALID_DCMD = 0x02,
127 MFI_STAT_INVALID_PARAMETER = 0x03,
128 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
129 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
130 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
131 MFI_STAT_APP_IN_USE = 0x07,
132 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
133 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
134 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
135 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
136 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
137 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
138 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
139 MFI_STAT_FLASH_BUSY = 0x0f,
140 MFI_STAT_FLASH_ERROR = 0x10,
141 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
142 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
143 MFI_STAT_FLASH_NOT_OPEN = 0x13,
144 MFI_STAT_FLASH_NOT_STARTED = 0x14,
145 MFI_STAT_FLUSH_FAILED = 0x15,
146 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
147 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
148 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
149 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
150 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
151 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
152 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
153 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
154 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
155 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
156 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
157 MFI_STAT_MFC_HW_ERROR = 0x21,
158 MFI_STAT_NO_HW_PRESENT = 0x22,
159 MFI_STAT_NOT_FOUND = 0x23,
160 MFI_STAT_NOT_IN_ENCL = 0x24,
161 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
162 MFI_STAT_PD_TYPE_WRONG = 0x26,
163 MFI_STAT_PR_DISABLED = 0x27,
164 MFI_STAT_ROW_INDEX_INVALID = 0x28,
165 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
166 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
167 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
168 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
169 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
170 MFI_STAT_SCSI_IO_FAILED = 0x2e,
171 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
172 MFI_STAT_SHUTDOWN_FAILED = 0x30,
173 MFI_STAT_TIME_NOT_SET = 0x31,
174 MFI_STAT_WRONG_STATE = 0x32,
175 MFI_STAT_LD_OFFLINE = 0x33,
176 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
177 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
178 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
179 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
180 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
181 MFI_STAT_INVALID_STATUS = 0xff
182 } mfi_status_t;
183
184 typedef enum {
185 MFI_EVT_CLASS_DEBUG = -2,
186 MFI_EVT_CLASS_PROGRESS = -1,
187 MFI_EVT_CLASS_INFO = 0,
188 MFI_EVT_CLASS_WARNING = 1,
189 MFI_EVT_CLASS_CRITICAL = 2,
190 MFI_EVT_CLASS_FATAL = 3,
191 MFI_EVT_CLASS_DEAD = 4
192 } mfi_evt_class_t;
193
194 typedef enum {
195 MFI_EVT_LOCALE_LD = 0x0001,
196 MFI_EVT_LOCALE_PD = 0x0002,
197 MFI_EVT_LOCALE_ENCL = 0x0004,
198 MFI_EVT_LOCALE_BBU = 0x0008,
199 MFI_EVT_LOCALE_SAS = 0x0010,
200 MFI_EVT_LOCALE_CTRL = 0x0020,
201 MFI_EVT_LOCALE_CONFIG = 0x0040,
202 MFI_EVT_LOCALE_CLUSTER = 0x0080,
203 MFI_EVT_LOCALE_ALL = 0xffff
204 } mfi_evt_locale_t;
205
206 typedef enum {
207 MR_EVT_ARGS_NONE = 0x00,
208 MR_EVT_ARGS_CDB_SENSE,
209 MR_EVT_ARGS_LD,
210 MR_EVT_ARGS_LD_COUNT,
211 MR_EVT_ARGS_LD_LBA,
212 MR_EVT_ARGS_LD_OWNER,
213 MR_EVT_ARGS_LD_LBA_PD_LBA,
214 MR_EVT_ARGS_LD_PROG,
215 MR_EVT_ARGS_LD_STATE,
216 MR_EVT_ARGS_LD_STRIP,
217 MR_EVT_ARGS_PD,
218 MR_EVT_ARGS_PD_ERR,
219 MR_EVT_ARGS_PD_LBA,
220 MR_EVT_ARGS_PD_LBA_LD,
221 MR_EVT_ARGS_PD_PROG,
222 MR_EVT_ARGS_PD_STATE,
223 MR_EVT_ARGS_PCI,
224 MR_EVT_ARGS_RATE,
225 MR_EVT_ARGS_STR,
226 MR_EVT_ARGS_TIME,
227 MR_EVT_ARGS_ECC
228 } mfi_evt_args;
229
230
231 #define MFI_MAX_PD_CHANNELS 2
232 #define MFI_MAX_PD_ARRAY 32
233 #define MFI_MAX_LD_CHANNELS 2
234 #define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
235 #define MFI_MAX_CHANNEL_DEVS 128
236 #define MFI_DEFAULT_ID -1
237 #define MFI_MAX_LUN 8
238 #define MFI_MAX_LD 64
239 #define MFI_MAX_SPAN 8
240 #define MFI_MAX_ARRAY_DEDICATED 16
241
242
243 struct mfi_sense {
244 uint8_t mse_data[MFI_SENSE_SIZE];
245 } __packed;
246
247
248 struct mfi_sg32 {
249 uint32_t addr;
250 uint32_t len;
251 } __packed;
252
253 struct mfi_sg64 {
254 uint64_t addr;
255 uint32_t len;
256 } __packed;
257
258 union mfi_sgl {
259 struct mfi_sg32 sg32[1];
260 struct mfi_sg64 sg64[1];
261 } __packed;
262
263
264 struct mfi_frame_header {
265 uint8_t mfh_cmd;
266 uint8_t mfh_sense_len;
267 uint8_t mfh_cmd_status;
268 uint8_t mfh_scsi_status;
269 uint8_t mfh_target_id;
270 uint8_t mfh_lun_id;
271 uint8_t mfh_cdb_len;
272 uint8_t mfh_sg_count;
273 uint32_t mfh_context;
274 uint32_t mfh_pad0;
275 uint16_t mfh_flags;
276 uint16_t mfh_timeout;
277 uint32_t mfh_data_len;
278 } __packed;
279
280 union mfi_sgl_frame {
281 struct mfi_sg32 sge32[8];
282 struct mfi_sg64 sge64[5];
283
284 } __packed;
285
286 struct mfi_init_frame {
287 struct mfi_frame_header mif_header;
288 uint32_t mif_qinfo_new_addr_lo;
289 uint32_t mif_qinfo_new_addr_hi;
290 uint32_t mif_qinfo_old_addr_lo;
291 uint32_t mif_qinfo_old_addr_hi;
292 uint32_t mif_reserved[6];
293 } __packed;
294
295
296 struct mfi_init_qinfo {
297 uint32_t miq_flags;
298 uint32_t miq_rq_entries;
299 uint32_t miq_rq_addr_lo;
300 uint32_t miq_rq_addr_hi;
301 uint32_t miq_pi_addr_lo;
302 uint32_t miq_pi_addr_hi;
303 uint32_t miq_ci_addr_lo;
304 uint32_t miq_ci_addr_hi;
305 } __packed;
306
307 #define MFI_IO_FRAME_SIZE 40
308 struct mfi_io_frame {
309 struct mfi_frame_header mif_header;
310 uint32_t mif_sense_addr_lo;
311 uint32_t mif_sense_addr_hi;
312 uint32_t mif_lba_lo;
313 uint32_t mif_lba_hi;
314 union mfi_sgl mif_sgl;
315 } __packed;
316
317 #define MFI_PASS_FRAME_SIZE 48
318 struct mfi_pass_frame {
319 struct mfi_frame_header mpf_header;
320 uint32_t mpf_sense_addr_lo;
321 uint32_t mpf_sense_addr_hi;
322 uint8_t mpf_cdb[16];
323 union mfi_sgl mpf_sgl;
324 } __packed;
325
326 #define MFI_DCMD_FRAME_SIZE 40
327 struct mfi_dcmd_frame {
328 struct mfi_frame_header mdf_header;
329 uint32_t mdf_opcode;
330 uint8_t mdf_mbox[MFI_MBOX_SIZE];
331 union mfi_sgl mdf_sgl;
332 } __packed;
333
334 struct mfi_abort_frame {
335 struct mfi_frame_header maf_header;
336 uint32_t maf_abort_context;
337 uint32_t maf_pad;
338 uint32_t maf_abort_mfi_addr_lo;
339 uint32_t maf_abort_mfi_addr_hi;
340 uint32_t maf_reserved[6];
341 } __packed;
342
343 struct mfi_smp_frame {
344 struct mfi_frame_header msf_header;
345 uint64_t msf_sas_addr;
346 union {
347 struct mfi_sg32 sg32[2];
348 struct mfi_sg64 sg64[2];
349 } msf_sgl;
350 } __packed;
351
352 struct mfi_stp_frame {
353 struct mfi_frame_header msf_header;
354 uint16_t msf_fis[10];
355 uint32_t msf_stp_flags;
356 union {
357 struct mfi_sg32 sg32[2];
358 struct mfi_sg64 sg64[2];
359 } msf_sgl;
360 } __packed;
361
362 union mfi_frame {
363 struct mfi_frame_header mfr_header;
364 struct mfi_init_frame mfr_init;
365 struct mfi_io_frame mfr_io;
366 struct mfi_pass_frame mfr_pass;
367 struct mfi_dcmd_frame mfr_dcmd;
368 struct mfi_abort_frame mfr_abort;
369 struct mfi_smp_frame mfr_smp;
370 struct mfi_stp_frame mfr_stp;
371 uint8_t mfr_bytes[MFI_FRAME_SIZE];
372 };
373
374 union mfi_evt_class_locale {
375 struct {
376 uint16_t locale;
377 uint8_t reserved;
378 int8_t class;
379 } __packed mec_members;
380
381 uint32_t mec_word;
382 } __packed;
383
384 struct mfi_evt_log_info {
385 uint32_t mel_newest_seq_num;
386 uint32_t mel_oldest_seq_num;
387 uint32_t mel_clear_seq_num;
388 uint32_t mel_shutdown_seq_num;
389 uint32_t mel_boot_seq_num;
390 } __packed;
391
392 struct mfi_progress {
393 uint16_t mp_progress;
394 uint16_t mp_elapsed_seconds;
395 } __packed;
396
397 struct mfi_evtarg_ld {
398 uint16_t mel_target_id;
399 uint8_t mel_ld_index;
400 uint8_t mel_reserved;
401 } __packed;
402
403 struct mfi_evtarg_pd {
404 uint16_t mep_device_id;
405 uint8_t mep_encl_index;
406 uint8_t mep_slot_number;
407 } __packed;
408
409 struct mfi_evt_detail {
410 uint32_t med_seq_num;
411 uint32_t med_time_stamp;
412 uint32_t med_code;
413 union mfi_evt_class_locale med_cl;
414 uint8_t med_arg_type;
415 uint8_t med_reserved1[15];
416
417 union {
418 struct {
419 struct mfi_evtarg_pd pd;
420 uint8_t cdb_length;
421 uint8_t sense_length;
422 uint8_t reserved[2];
423 uint8_t cdb[16];
424 uint8_t sense[64];
425 } __packed cdb_sense;
426
427 struct mfi_evtarg_ld ld;
428
429 struct {
430 struct mfi_evtarg_ld ld;
431 uint64_t count;
432 } __packed ld_count;
433
434 struct {
435 uint64_t lba;
436 struct mfi_evtarg_ld ld;
437 } __packed ld_lba;
438
439 struct {
440 struct mfi_evtarg_ld ld;
441 uint32_t prev_owner;
442 uint32_t new_owner;
443 } __packed ld_owner;
444
445 struct {
446 uint64_t ld_lba;
447 uint64_t pd_lba;
448 struct mfi_evtarg_ld ld;
449 struct mfi_evtarg_pd pd;
450 } __packed ld_lba_pd_lba;
451
452 struct {
453 struct mfi_evtarg_ld ld;
454 struct mfi_progress prog;
455 } __packed ld_prog;
456
457 struct {
458 struct mfi_evtarg_ld ld;
459 uint32_t prev_state;
460 uint32_t new_state;
461 } __packed ld_state;
462
463 struct {
464 uint64_t strip;
465 struct mfi_evtarg_ld ld;
466 } __packed ld_strip;
467
468 struct mfi_evtarg_pd pd;
469
470 struct {
471 struct mfi_evtarg_pd pd;
472 uint32_t err;
473 } __packed pd_err;
474
475 struct {
476 uint64_t lba;
477 struct mfi_evtarg_pd pd;
478 } __packed pd_lba;
479
480 struct {
481 uint64_t lba;
482 struct mfi_evtarg_pd pd;
483 struct mfi_evtarg_ld ld;
484 } __packed pd_lba_ld;
485
486 struct {
487 struct mfi_evtarg_pd pd;
488 struct mfi_progress prog;
489 } __packed pd_prog;
490
491 struct {
492 struct mfi_evtarg_pd pd;
493 uint32_t prev_state;
494 uint32_t new_state;
495 } __packed pd_state;
496
497 struct {
498 uint16_t vendor_id;
499 uint16_t device_id;
500 uint16_t subvendor_id;
501 uint16_t subdevice_id;
502 } __packed pci;
503
504 uint32_t rate;
505 char str[96];
506
507 struct {
508 uint32_t rtc;
509 uint32_t elapsed_seconds;
510 } __packed time;
511
512 struct {
513 uint32_t ecar;
514 uint32_t elog;
515 char str[64];
516 } __packed ecc;
517
518 uint8_t b[96];
519 uint16_t s[48];
520 uint32_t w[24];
521 uint64_t d[12];
522 } args;
523
524 char med_description[128];
525 } __packed;
526
527
528 struct mfi_ctrl_props {
529 uint16_t mcp_seq_num;
530 uint16_t mcp_pred_fail_poll_interval;
531 uint16_t mcp_intr_throttle_cnt;
532 uint16_t mcp_intr_throttle_timeout;
533 uint8_t mcp_rebuild_rate;
534 uint8_t mcp_patrol_read_rate;
535 uint8_t mcp_bgi_rate;
536 uint8_t mcp_cc_rate;
537 uint8_t mcp_recon_rate;
538 uint8_t mcp_cache_flush_interval;
539 uint8_t mcp_spinup_drv_cnt;
540 uint8_t mcp_spinup_delay;
541 uint8_t mcp_cluster_enable;
542 uint8_t mcp_coercion_mode;
543 uint8_t mcp_alarm_enable;
544 uint8_t mcp_disable_auto_rebuild;
545 uint8_t mcp_disable_battery_warn;
546 uint8_t mcp_ecc_bucket_size;
547 uint16_t mcp_ecc_bucket_leak_rate;
548 uint8_t mcp_restore_hotspare_on_insertion;
549 uint8_t mcp_expose_encl_devices;
550 uint8_t mcp_reserved[38];
551 } __packed;
552
553
554 struct mfi_info_pci {
555 uint16_t mip_vendor;
556 uint16_t mip_device;
557 uint16_t mip_subvendor;
558 uint16_t mip_subdevice;
559 uint8_t mip_reserved[24];
560 } __packed;
561
562
563 struct mfi_info_host {
564 uint8_t mih_type;
565 #define MFI_INFO_HOST_PCIX 0x01
566 #define MFI_INFO_HOST_PCIE 0x02
567 #define MFI_INFO_HOST_ISCSI 0x04
568 #define MFI_INFO_HOST_SAS3G 0x08
569 uint8_t mih_reserved[6];
570 uint8_t mih_port_count;
571 uint64_t mih_port_addr[8];
572 } __packed;
573
574
575 struct mfi_info_device {
576 uint8_t mid_type;
577 #define MFI_INFO_DEV_SPI 0x01
578 #define MFI_INFO_DEV_SAS3G 0x02
579 #define MFI_INFO_DEV_SATA1 0x04
580 #define MFI_INFO_DEV_SATA3G 0x08
581 uint8_t mid_reserved[6];
582 uint8_t mid_port_count;
583 uint64_t mid_port_addr[8];
584 } __packed;
585
586
587 struct mfi_info_component {
588 char mic_name[8];
589 char mic_version[32];
590 char mic_build_date[16];
591 char mic_build_time[16];
592 } __packed;
593
594
595 struct mfi_ctrl_info {
596 struct mfi_info_pci mci_pci;
597 struct mfi_info_host mci_host;
598 struct mfi_info_device mci_device;
599
600
601 uint32_t mci_image_check_word;
602 uint32_t mci_image_component_count;
603 struct mfi_info_component mci_image_component[8];
604
605
606 uint32_t mci_pending_image_component_count;
607 struct mfi_info_component mci_pending_image_component[8];
608
609 uint8_t mci_max_arms;
610 uint8_t mci_max_spans;
611 uint8_t mci_max_arrays;
612 uint8_t mci_max_lds;
613 char mci_product_name[80];
614 char mci_serial_number[32];
615 uint32_t mci_hw_present;
616 #define MFI_INFO_HW_BBU 0x01
617 #define MFI_INFO_HW_ALARM 0x02
618 #define MFI_INFO_HW_NVRAM 0x04
619 #define MFI_INFO_HW_UART 0x08
620 uint32_t mci_current_fw_time;
621 uint16_t mci_max_cmds;
622 uint16_t mci_max_sg_elements;
623 uint32_t mci_max_request_size;
624 uint16_t mci_lds_present;
625 uint16_t mci_lds_degraded;
626 uint16_t mci_lds_offline;
627 uint16_t mci_pd_present;
628 uint16_t mci_pd_disks_present;
629 uint16_t mci_pd_disks_pred_failure;
630 uint16_t mci_pd_disks_failed;
631 uint16_t mci_nvram_size;
632 uint16_t mci_memory_size;
633 uint16_t mci_flash_size;
634 uint16_t mci_ram_correctable_errors;
635 uint16_t mci_ram_uncorrectable_errors;
636 uint8_t mci_cluster_allowed;
637 uint8_t mci_cluster_active;
638 uint16_t mci_max_strips_per_io;
639
640 uint32_t mci_raid_levels;
641 #define MFI_INFO_RAID_0 0x01
642 #define MFI_INFO_RAID_1 0x02
643 #define MFI_INFO_RAID_5 0x04
644 #define MFI_INFO_RAID_1E 0x08
645 #define MFI_INFO_RAID_6 0x10
646
647 uint32_t mci_adapter_ops;
648 #define MFI_INFO_AOPS_RBLD_RATE 0x0001
649 #define MFI_INFO_AOPS_CC_RATE 0x0002
650 #define MFI_INFO_AOPS_BGI_RATE 0x0004
651 #define MFI_INFO_AOPS_RECON_RATE 0x0008
652 #define MFI_INFO_AOPS_PATROL_RATE 0x0010
653 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
654 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
655 #define MFI_INFO_AOPS_BBU 0x0080
656 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
657 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
658 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
659 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
660 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
661 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
662 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
663
664 uint32_t mci_ld_ops;
665 #define MFI_INFO_LDOPS_READ_POLICY 0x01
666 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02
667 #define MFI_INFO_LDOPS_IO_POLICY 0x04
668 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
669 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
670
671 struct {
672 uint8_t min;
673 uint8_t max;
674 uint8_t reserved[2];
675 } __packed mci_stripe_sz_ops;
676
677 uint32_t mci_pd_ops;
678 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
679 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
680 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
681
682 uint32_t mci_pd_mix_support;
683 #define MFI_INFO_PDMIX_SAS 0x01
684 #define MFI_INFO_PDMIX_SATA 0x02
685 #define MFI_INFO_PDMIX_ENCL 0x04
686 #define MFI_INFO_PDMIX_LD 0x08
687 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
688
689 uint8_t mci_ecc_bucket_count;
690 uint8_t mci_reserved2[11];
691 struct mfi_ctrl_props mci_properties;
692 char mci_package_version[0x60];
693 uint8_t mci_pad[0x800 - 0x6a0];
694 } __packed;
695
696
697 struct mfi_ld {
698 uint8_t mld_target;
699 uint8_t mld_res;
700 uint16_t mld_seq;
701 } __packed;
702
703 struct mfi_ld_list {
704 uint32_t mll_no_ld;
705 uint32_t mll_res;
706 struct {
707 struct mfi_ld mll_ld;
708 uint8_t mll_state;
709 #define MFI_LD_OFFLINE 0x00
710 #define MFI_LD_PART_DEGRADED 0x01
711 #define MFI_LD_DEGRADED 0x02
712 #define MFI_LD_ONLINE 0x03
713 uint8_t mll_res2;
714 uint8_t mll_res3;
715 uint8_t mll_res4;
716 u_quad_t mll_size;
717 } mll_list[MFI_MAX_LD];
718 } __packed;
719
720
721 struct mfi_ld_prop {
722 struct mfi_ld mlp_ld;
723 char mlp_name[16];
724 uint8_t mlp_cache_policy;
725 uint8_t mlp_acces_policy;
726 uint8_t mlp_diskcache_policy;
727 uint8_t mlp_cur_cache_policy;
728 uint8_t mlp_disable_bgi;
729 uint8_t mlp_res[7];
730 } __packed;
731
732 struct mfi_ld_parm {
733 uint8_t mpa_pri_raid;
734 #define MFI_DDF_PRL_RAID0 0x00
735 #define MFI_DDF_PRL_RAID1 0x01
736 #define MFI_DDF_PRL_RAID3 0x03
737 #define MFI_DDF_PRL_RAID4 0x04
738 #define MFI_DDF_PRL_RAID5 0x05
739 #define MFI_DDF_PRL_RAID1E 0x11
740 #define MFI_DDF_PRL_JBOD 0x0f
741 #define MFI_DDF_PRL_CONCAT 0x1f
742 #define MFI_DDF_PRL_RAID5E 0x15
743 #define MFI_DDF_PRL_RAID5EE 0x25
744 #define MFI_DDF_PRL_RAID6 0x16
745 uint8_t mpa_raid_qual;
746 uint8_t mpa_sec_raid;
747 #define MFI_DDF_SRL_STRIPED 0x00
748 #define MFI_DDF_SRL_MIRRORED 0x01
749 #define MFI_DDF_SRL_CONCAT 0x02
750 #define MFI_DDF_SRL_SPANNED 0x03
751 uint8_t mpa_stripe_size;
752 uint8_t mpa_no_drv_per_span;
753 uint8_t mpa_span_depth;
754 uint8_t mpa_state;
755 uint8_t mpa_init_state;
756 uint8_t mpa_res[24];
757 } __packed;
758
759 struct mfi_ld_span {
760 u_quad_t mls_start_block;
761 u_quad_t mls_no_blocks;
762 uint16_t mls_index;
763 uint8_t mls_res[6];
764 } __packed;
765
766 struct mfi_ld_cfg {
767 struct mfi_ld_prop mlc_prop;
768 struct mfi_ld_parm mlc_parm;
769 struct mfi_ld_span mlc_span[MFI_MAX_SPAN];
770 } __packed;
771
772 struct mfi_ld_progress {
773 uint32_t mlp_in_prog;
774 #define MFI_LD_PROG_CC 0x01
775 #define MFI_LD_PROG_BGI 0x02
776 #define MFI_LD_PROG_FGI 0x04
777 #define MFI_LD_PROG_RECONSTRUCT 0x08
778 struct mfi_progress mlp_cc;
779 struct mfi_progress mlp_bgi;
780 struct mfi_progress mlp_fgi;
781 struct mfi_progress mlp_reconstruct;
782 struct mfi_progress mlp_res[4];
783 } __packed;
784
785 struct mfi_ld_details {
786 struct mfi_ld_cfg mld_cfg;
787 u_quad_t mld_size;
788 struct mfi_ld_progress mld_progress;
789 uint16_t mld_clust_own_id;
790 uint8_t mld_res1;
791 uint8_t mld_res2;
792 uint8_t mld_inq_page83[64];
793 uint8_t mld_res[16];
794 } __packed;
795
796
797 struct mfi_pd_address {
798 uint16_t mpa_pd_id;
799 uint16_t mpa_enc_id;
800 uint8_t mpa_enc_index;
801 uint8_t mpa_enc_slot;
802 uint8_t mpa_scsi_type;
803 uint8_t mpa_port;
804 u_quad_t mpa_sas_address[2];
805 } __packed;
806
807 struct mfi_pd_list {
808 uint32_t mpl_size;
809 uint32_t mpl_no_pd;
810 struct mfi_pd_address mpl_address[1];
811 } __packed;
812 #define MFI_PD_LIST_SIZE (256 * sizeof(struct mfi_pd_address) + 8)
813
814 struct mfi_pd {
815 uint16_t mfp_id;
816 uint16_t mfp_seq;
817 } __packed;
818
819 struct mfi_pd_progress {
820 uint32_t mfp_in_prog;
821 #define MFI_PD_PROG_RBLD 0x01
822 #define MFI_PD_PROG_PR 0x02
823 #define MFI_PD_PROG_CLEAR 0x04
824 struct mfi_progress mfp_rebuild;
825 struct mfi_progress mfp_patrol_read;
826 struct mfi_progress mfp_clear;
827 struct mfi_progress mfp_res[4];
828 } __packed;
829
830 struct mfi_pd_details {
831 struct mfi_pd mpd_pd;
832 uint8_t mpd_inq_data[96];
833 uint8_t mpd_inq_page83[64];
834 uint8_t mpd_no_support;
835 uint8_t mpd_scsy_type;
836 uint8_t mpd_port;
837 uint8_t mpd_speed;
838 uint32_t mpd_mediaerr_cnt;
839 uint32_t mpd_othererr_cnt;
840 uint32_t mpd_predfail_cnt;
841 uint32_t mpd_last_pred_event;
842 uint16_t mpd_fw_state;
843 uint8_t mpd_rdy_for_remove;
844 uint8_t mpd_link_speed;
845 uint32_t mpd_ddf_state;
846 #define MFI_DDF_GUID_FORCED 0x01
847 #define MFI_DDF_PART_OF_VD 0x02
848 #define MFI_DDF_GLOB_HOTSPARE 0x04
849 #define MFI_DDF_HOTSPARE 0x08
850 #define MFI_DDF_FOREIGN 0x10
851 #define MFI_DDF_TYPE_MASK 0xf000
852 #define MFI_DDF_TYPE_UNKNOWN 0x0000
853 #define MFI_DDF_TYPE_PAR_SCSI 0x1000
854 #define MFI_DDF_TYPE_SAS 0x2000
855 #define MFI_DDF_TYPE_SATA 0x3000
856 #define MFI_DDF_TYPE_FC 0x4000
857 struct {
858 uint8_t mpp_cnt;
859 uint8_t mpp_severed;
860 uint8_t mpp_res[6];
861 u_quad_t mpp_sas_addr[4];
862 } __packed mpd_path;
863 u_quad_t mpd_size;
864 u_quad_t mpd_no_coerce_size;
865 u_quad_t mpd_coerce_size;
866 uint16_t mpd_enc_id;
867 uint8_t mpd_enc_idx;
868 uint8_t mpd_enc_slot;
869 struct mfi_pd_progress mpd_progress;
870 uint8_t mpd_bblock_full;
871 uint8_t mpd_unusable;
872 uint8_t mpd_res[218];
873 } __packed;
874
875
876 struct mfi_array {
877 u_quad_t mar_smallest_pd;
878 uint8_t mar_no_disk;
879 uint8_t mar_res1;
880 uint16_t mar_array_ref;
881 uint8_t mar_res2[20];
882 struct {
883 struct mfi_pd mar_pd;
884 uint16_t mar_pd_state;
885 #define MFI_PD_UNCONFIG_GOOD 0x00
886 #define MFI_PD_UNCONFIG_BAD 0x01
887 #define MFI_PD_HOTSPARE 0x02
888 #define MFI_PD_OFFLINE 0x10
889 #define MFI_PD_FAILED 0x11
890 #define MFI_PD_REBUILD 0x14
891 #define MFI_PD_ONLINE 0x18
892 uint8_t mar_enc_pd;
893 uint8_t mar_enc_slot;
894 } pd[MFI_MAX_PD_ARRAY];
895 } __packed;
896
897 struct mfi_hotspare {
898 struct mfi_pd mhs_pd;
899 uint8_t mhs_type;
900 #define MFI_PD_HS_DEDICATED 0x01
901 #define MFI_PD_HS_REVERTIBLE 0x02
902 #define MFI_PD_HS_ENC_AFFINITY 0x04
903 uint8_t mhs_res[2];
904 uint8_t mhs_array_max;
905 uint16_t mhs_array_ref[MFI_MAX_ARRAY_DEDICATED];
906 } __packed;
907
908 struct mfi_conf {
909 uint32_t mfc_size;
910 uint16_t mfc_no_array;
911 uint16_t mfc_array_size;
912 uint16_t mfc_no_ld;
913 uint16_t mfc_ld_size;
914 uint16_t mfc_no_hs;
915 uint16_t mfc_hs_size;
916 uint8_t mfc_res[16];
917
918
919
920
921
922
923
924
925 struct mfi_array mfc_array[1];
926 struct mfi_ld_cfg mfc_ld[1];
927 struct mfi_hotspare mfc_hs[1];
928 } __packed;