1 /* $OpenBSD: cd1190reg.h,v 1.3 2003/10/21 18:58:49 jmc Exp $ */
2
3 /*
4 * Copyright (c) 1998 Iain Hibbert.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name Iain Hibbert may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 /*
31 * Definitions for Cirrus Logic CD1190 parallel chips.
32 */
33
34 /* ACK Width Register */
35 #define CD1190_AWR 0x03
36
37 /* Controller Command Register */
38 #define CD1190_CCR 0x0b
39 #define CD1190_CCR_CGC (1<<7) /* Change Global Config Command */
40 #define CD1190_CCR_CGC_RESET (1<<0) /* CGC Reset Command */
41 #define CD1190_CCR_PAR (1<<6) /* Parallel Command */
42 #define CD1190_CCR_PAR_DISABLE (1<<2) /* PAR Parallel Disable */
43 #define CD1190_CCR_PAR_FLUSH (1<<1) /* PAR Flush FIFO */
44 #define CD1190_CCR_PAR_ENABLE (1<<0) /* PAR Parallel Enable */
45 #define CD1190_CCR_SIG (1<<5) /* Signal Command */
46 #define CD1190_CCR_SIG_SET_BUSY (1<<2) /* SIG Set Busy Output */
47 #define CD1190_CCR_SIG_ACK (1<<1) /* SIG Pulse ACK Output */
48 #define CD1190_CCR_SIG_CLR_BUSY (1<<0) /* SIG Clear Busy Output */
49 #define CD1190_CCR_TIM (1<<4) /* Timer Command */
50 #define CD1190_CCR_TIM_ENABLE (1<<3) /* Timer Enabled */
51
52 /* Data Time-0ut Register */
53 #define CD1190_DTR 0x09
54
55 /* End Of Service Request Register */
56 #define CD1190_ESR 0x10
57
58 /* FIFO Count Register */
59 #define CD1190_FCR 0x0e
60
61 /* FIFO Data Register */
62 #define CD1190_FDR 0x12
63
64 /* Firmware Revision Register */
65 #define CD1190_FRR 0x0f
66
67 /* FIFO Threshold Register */
68 #define CD1190_FTR 0x08
69
70 /* Global Config Register */
71 #define CD1190_GCR 0x0a
72 #define CD1190_GCR_NOACK (1<<2) /* NO-ACK handshaking */
73 #define CD1190_GCR_MODE (1<<1) /* Peripheral/Controller Mode */
74 #define CD1190_GCR_DIR (1<<0) /* Input/Output Direction */
75
76 /* defines for variable CD1190_IO */
77 #define CD1190_CO 0x00
78 #define CD1190_CI 0x01
79 #define CD1190_PO 0x02
80 #define CD1190_PI 0x03
81
82 /* Interrupt Config Register */
83 #define CD1190_ICR 0x01
84 #define CD1190_ICR_ENABLE (1<<7) /* Enable Interrupts */
85 #define CD1190_ICR_ACK (1<<3) /* Enable: Unsolicited ACK */
86 #define CD1190_ICR_FIFO (1<<2) /* Enable: FIFO Thresh/Time */
87 #define CD1190_ICR_SIGNAL (1<<1) /* Enable: Signal Status */
88 #define CD1190_ICR_TIMER (1<<0) /* Enable: Timer Expired */
89
90 /* Interrupt Status Register */
91 #define CD1190_ISR 0x0c
92 #define CD1190_ISR_INTERRUPT (1<<7) /* Interrupt Has Occurred */
93 #define CD1190_ISR_ACK (1<<3) /* Unsolicited ACK */
94 #define CD1190_ISR_FIFO (1<<2) /* FIFO Thresh/Time */
95 #define CD1190_ISR_SIGNAL (1<<1) /* Signal Status */
96 #define CD1190_ISR_TIMER (1<<0) /* Timer Expired */
97
98 /* Interrupt Vector Register */
99 #define CD1190_IVR 0x00
100
101 /* Parallel Status Register */
102 #define CD1190_PSR 0x1c
103 #define CD1190_PSR_ENP (1<<7) /* Parallel Enabled */
104 #define CD1190_PSR_BUSY (1<<6) /* Parallel Busy */
105 #define CD1190_PSR_ACK (1<<5) /* Parallel Acknowledge */
106 #define CD1190_PSR_STATUS (CD1190_PSR_ENP | CD1190_PSR_BUSY)
107 #define CD1190_PSR_NORMAL CD1190_PSR_ENP
108
109 /* Signal Control Register */
110 #define CD1190_SCR 0x1e
111 #define CD1190_SCR_WRRD (1<<7) /* Read Only: Write/Read */
112 #define CD1190_SCR_IP3 (1<<6) /* Read Only: Input Line 3 */
113 #define CD1190_SCR_IP2 (1<<5) /* Read Only: Input Line 2 */
114 #define CD1190_SCR_IP1 (1<<4) /* Read Only: Input Line 1 */
115 #define CD1190_SCR_WR_WRRD (1<<3) /* Write/Read */
116 #define CD1190_SCR_OP3 (1<<2) /* Output Line 3 */
117 #define CD1190_SCR_OP2 (1<<1) /* Output Line 2 */
118 #define CD1190_SCR_OP1 (1<<0) /* Output Line 1 */
119
120 /* Input signals
121 *
122 * IP3 - *ERROR
123 * IP2 - PAPER EMPTY / FAULT
124 * IP1 - SELECT
125 * WRRD - AFD
126 * OP3 - SLIN
127 * OP2 - *INIT / *RESET
128 * OP1 - N/A
129 */
130 #define CD1190_SCR_NOERROR CD1190_SCR_IP3 /* Printer Error (active low) */
131 #define CD1190_SCR_PE CD1190_SCR_IP2 /* Paper Empty */
132 #define CD1190_SCR_SELECT CD1190_SCR_IP1 /* Printer Select */
133
134 #define CD1190_SCR_STATUS (CD1190_SCR_IP3 | CD1190_SCR_IP2 | CD1190_SCR_IP1)
135
136 /* Outout signals - Active High?
137 *
138 * IP3 - SLIN
139 * IP2 - *INIT / *RESET
140 * IP1 - N/A
141 * WRRD - AFD
142 * OP3 - *ERROR
143 * OP2 - SELECT
144 * OP1 - PAPER EMPTY / FAULT
145 */
146 #define CD1190_SCR_RESET CD1190_SCR_OP2
147 #define CD1190_SCR_SEL_IN CD1190_SCR_OP3
148
149 /* Specification Register ZEROes */
150 #define CD1190_SR0 0x06
151 #define CD1190_SR0_WRRD (1<<7) /* WR/RD 1 to 0 Change */
152 #define CD1190_SR0_IP3 (1<<6) /* IP3 1 to 0 Change */
153 #define CD1190_SR0_IP2 (1<<5) /* IP2 1 to 0 Change */
154 #define CD1190_SR0_IP1 (1<<4) /* IP1 1 to 0 Change */
155
156 /* Specification Register ONEs */
157 #define CD1190_SR1 0x07
158 #define CD1190_SR1_WRRD (1<<7) /* WR/RD 0 to 1 Change */
159 #define CD1190_SR1_IP3 (1<<6) /* IP3 0 to 1 Change */
160 #define CD1190_SR1_IP2 (1<<5) /* IP2 0 to 1 Change */
161 #define CD1190_SR1_IP1 (1<<4) /* IP1 0 to 1 Change */
162
163 /* Signal Status Register */
164 #define CD1190_SSR 0x0d
165 #define CD1190_SSR_WRRD (1<<7) /* WR/RD Change */
166 #define CD1190_SSR_IP3 (1<<6) /* IP3 Change */
167 #define CD1190_SSR_IP2 (1<<5) /* IP2 Change */
168 #define CD1190_SSR_IP1 (1<<4) /* IP1 Change */
169
170 /* Strobe Width Register */
171 #define CD1190_SWR 0x02
172
173 /* Timer Multipler Register */
174 #define CD1190_TMR 0x05
175
176 /* Timer Prescale Register */
177 #define CD1190_TPR 0x04