1 /* $OpenBSD: awireg.h,v 1.4 2001/07/04 09:02:59 niklas Exp $ */
2 /* $NetBSD: awireg.h,v 1.3 2000/03/22 11:22:22 onoe Exp $ */
3
4 /*-
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Bill Sommerfeld
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * The firmware typically loaded onto Am79C930-based 802.11 interfaces
42 * uses a 32k or larger shared memory buffer to communicate with the
43 * host.
44 *
45 * Depending on the exact configuration of the device, this buffer may
46 * either be mapped into PCMCIA memory space, or accessible a byte at
47 * a type through PCMCIA I/O space.
48 *
49 * This header defines offsets into this shared memory.
50 */
51
52
53 /*
54 * LAST_TXD block. 5 32-bit words.
55 *
56 * There are five different output queues; this defines pointers to
57 * the last completed descriptor for each one.
58 */
59 #define AWI_LAST_TXD 0x3ec /* last completed Tx Descr */
60
61 #define AWI_LAST_BCAST_TXD AWI_LAST_TXD+0
62 #define AWI_LAST_MGT_TXD AWI_LAST_TXD+4
63 #define AWI_LAST_DATA_TXD AWI_LAST_TXD+8
64 #define AWI_LAST_PS_POLL_TXD AWI_LAST_TXD+12
65 #define AWI_LAST_CF_POLL_TXD AWI_LAST_TXD+16
66
67 /*
68 * Banner block; null-terminated string.
69 *
70 * The doc says it contains
71 * "PCnetMobile:v2.00 mmddyy APIx.x\0"
72 */
73
74 #define AWI_BANNER 0x480 /* Version string */
75 #define AWI_BANNER_LEN 0x20
76
77 /*
78 * Command block protocol:
79 * write command byte to a zero value.
80 * write command status to a zero value.
81 * write arguments to AWI_COMMAND_PARAMS
82 * write command byte to a non-zero value.
83 * wait for command status to be non-zero.
84 * write command byte to a zero value.
85 * write command status to a zero value.
86 */
87
88 #define AWI_CMD 0x4a0 /* Command opcode byte */
89
90 #define AWI_CMD_IDLE 0x0
91 #define AWI_CMD_NOP 0x1
92
93 #define AWI_CMD_SET_MIB 0x2
94 #define AWI_CMD_GET_MIB 0x9
95
96 #define AWI_CA_MIB_TYPE 0x0
97 #define AWI_CA_MIB_SIZE 0x1
98 #define AWI_CA_MIB_INDEX 0x2
99 #define AWI_CA_MIB_DATA 0x4
100
101 #define AWI_MIB_LOCAL 0x0
102 #define AWI_MIB_ADDR 0x2
103 #define AWI_MIB_MAC 0x3
104 #define AWI_MIB_STAT 0x4
105 #define AWI_MIB_MGT 0x5
106 #define AWI_MIB_DRVR 0x6
107 #define AWI_MIB_PHY 0x7
108
109
110 #define AWI_CMD_INIT_TX 0x3
111
112 #define AWI_CA_TX_LEN 0x14
113 #define AWI_CA_TX_DATA 0x0
114 #define AWI_CA_TX_MGT 0x4
115 #define AWI_CA_TX_BCAST 0x8
116 #define AWI_CA_TX_PS 0xc
117 #define AWI_CA_TX_CF 0x10
118
119 #define AWI_CMD_FLUSH_TX 0x4
120
121 #define AWI_CA_FTX_LEN 0x5
122 #define AWI_CA_FTX_DATA 0x0
123 #define AWI_CA_FTX_MGT 0x1
124 #define AWI_CA_FTX_BCAST 0x2
125 #define AWI_CA_FTX_PS 0x3
126 #define AWI_CA_FTX_CF 0x4
127
128 #define AWI_CMD_INIT_RX 0x5
129 #define AWI_CA_IRX_LEN 0x8
130 #define AWI_CA_IRX_DATA_DESC 0x0 /* return */
131 #define AWI_CA_IRX_PS_DESC 0x4 /* return */
132
133 #define AWI_CMD_KILL_RX 0x6
134
135 #define AWI_CMD_SLEEP 0x7
136 #define AWI_CA_SLEEP_LEN 0x8
137 #define AWI_CA_WAKEUP 0x0 /* uint64 */
138
139 #define AWI_CMD_WAKE 0x8
140
141 #define AWI_CMD_SCAN 0xa
142 #define AWI_CA_SCAN_LEN 0x6
143 #define AWI_CA_SCAN_DURATION 0x0
144 #define AWI_CA_SCAN_SET 0x2
145 #define AWI_CA_SCAN_PATTERN 0x3
146 #define AWI_CA_SCAN_IDX 0x4
147 #define AWI_CA_SCAN_SUSP 0x5
148
149 #define AWI_CMD_SYNC 0xb
150 #define AWI_CA_SYNC_LEN 0x14
151 #define AWI_CA_SYNC_SET 0x0
152 #define AWI_CA_SYNC_PATTERN 0x1
153 #define AWI_CA_SYNC_IDX 0x2
154 #define AWI_CA_SYNC_STARTBSS 0x3
155 #define AWI_CA_SYNC_DWELL 0x4
156 #define AWI_CA_SYNC_MBZ 0x6
157 #define AWI_CA_SYNC_TIMESTAMP 0x8
158 #define AWI_CA_SYNC_REFTIME 0x10
159
160 #define AWI_CMD_RESUME 0xc
161
162 #define AWI_CMD_STATUS 0x4a1 /* Command status */
163
164 #define AWI_STAT_IDLE 0x0
165 #define AWI_STAT_OK 0x1
166 #define AWI_STAT_BADCMD 0x2
167 #define AWI_STAT_BADPARM 0x3
168 #define AWI_STAT_NOTIMP 0x4
169 #define AWI_STAT_BADRES 0x5
170 #define AWI_STAT_BADMODE 0x6
171
172 #define AWI_ERROR_OFFSET 0x4a2 /* Offset to erroneous parameter */
173 #define AWI_CMD_PARAMS 0x4a4 /* Command parameters */
174
175 #define AWI_CSB 0x4f0 /* Control/Status block */
176
177 #define AWI_SELFTEST 0x4f0
178
179 #define AWI_SELFTEST_INIT 0x00 /* initial */
180 #define AWI_SELFTEST_FIRMCKSUM 0x01 /* firmware cksum running */
181 #define AWI_SELFTEST_HARDWARE 0x02 /* hardware tests running */
182 #define AWI_SELFTEST_MIB 0x03 /* mib initializing */
183
184 #define AWI_SELFTEST_MIB_FAIL 0xfa
185 #define AWI_SELFTEST_RADIO_FAIL 0xfb
186 #define AWI_SELFTEST_MAC_FAIL 0xfc
187 #define AWI_SELFTEST_FLASH_FAIL 0xfd
188 #define AWI_SELFTEST_RAM_FAIL 0xfe
189 #define AWI_SELFTEST_PASSED 0xff
190
191 #define AWI_STA_STATE 0x4f1
192
193 #define AWI_STA_AP 0x20 /* acting as AP */
194 #define AWI_STA_NOPSP 0x10 /* Power Saving disabled */
195 #define AWI_STA_DOZE 0x08 /* about to go to sleep */
196 #define AWI_STA_PSP 0x04 /* enable PSP */
197 #define AWI_STA_RXEN 0x02 /* enable RX */
198 #define AWI_STA_TXEN 0x01 /* enable TX */
199
200 #define AWI_INTSTAT 0x4f3
201 #define AWI_INTMASK 0x4f4
202
203 /* Bits in AWI_INTSTAT/AWI_INTMASK */
204
205 #define AWI_INT_GROGGY 0x80 /* about to wake up */
206 #define AWI_INT_CFP_ENDING 0x40 /* cont. free period ending */
207 #define AWI_INT_DTIM 0x20 /* beacon outgoing */
208 #define AWI_INT_CFP_START 0x10 /* cont. free period starting */
209 #define AWI_INT_SCAN_CMPLT 0x08 /* scan complete */
210 #define AWI_INT_TX 0x04 /* tx done */
211 #define AWI_INT_RX 0x02 /* rx done */
212 #define AWI_INT_CMD 0x01 /* cmd done */
213
214 /*
215 * The following are used to implement a locking protocol between host
216 * and MAC to protect the interrupt status and mask fields.
217 *
218 * driver: read lockout_host byte; if zero, set lockout_mac to non-zero,
219 * then reread lockout_host byte; if still zero, host has lock.
220 * if non-zero, clear lockout_mac, loop.
221 */
222
223 #define AWI_LOCKOUT_MAC 0x4f5
224 #define AWI_LOCKOUT_HOST 0x4f6
225
226
227 #define AWI_INTSTAT2 0x4f7
228 #define AWI_INTMASK2 0x4fd
229
230 /* Bits in AWI_INTSTAT2/INTMASK2 */
231 #define AWI_INT2_RXMGT 0x80 /* mgt/ps received */
232 #define AWI_INT2_RXDATA 0x40 /* data received */
233 #define AWI_INT2_TXMGT 0x10 /* mgt tx done */
234 #define AWI_INT2_TXCF 0x08 /* CF tx done */
235 #define AWI_INT2_TXPS 0x04 /* PS tx done */
236 #define AWI_INT2_TXBCAST 0x02 /* Broadcast tx done */
237 #define AWI_INT2_TXDATA 0x01 /* data tx done */
238
239 #define AWI_DIS_PWRDN 0x4fc /* disable powerdown if set */
240
241 #define AWI_DRIVERSTATE 0x4fe /* driver state */
242
243 #define AWI_DRV_STATEMASK 0x0f
244
245 #define AWI_DRV_RESET 0x0
246 #define AWI_DRV_INFSY 0x1 /* inf synced */
247 #define AWI_DRV_ADHSC 0x2 /* adhoc scan */
248 #define AWI_DRV_ADHSY 0x3 /* adhoc synced */
249 #define AWI_DRV_INFSC 0x4 /* inf scanning */
250 #define AWI_DRV_INFAUTH 0x5 /* inf authed */
251 #define AWI_DRV_INFASSOC 0x6 /* inf associated */
252 #define AWI_DRV_INFTOSS 0x7 /* inf handoff */
253 #define AWI_DRV_APNONE 0x8 /* AP activity: no assoc */
254 #define AWI_DRV_APQUIET 0xc /* AP: >=one assoc, no traffic */
255 #define AWI_DRV_APLO 0xd /* AP: >=one assoc, light tfc */
256 #define AWI_DRV_APMED 0xe /* AP: >=one assoc, mod tfc */
257 #define AWI_DRV_APHIGH 0xf /* AP: >=one assoc, heavy tfc */
258
259 #define AWI_DRV_AUTORXLED 0x10
260 #define AWI_DRV_AUTOTXLED 0x20
261 #define AWI_DRV_RXLED 0x40
262 #define AWI_DRV_TXLED 0x80
263
264 #define AWI_VBM 0x500 /* Virtual Bit Map */
265
266 #define AWI_BUFFERS 0x600 /* Buffers */
267 #define AWI_BUFFERS_END 0x6000
268
269 /*
270 * Receive descriptors; there are a linked list of these chained
271 * through the "NEXT" fields, starting from XXX
272 */
273
274 #define AWI_RXD_SIZE 0x18
275
276 #define AWI_RXD_NEXT 0x4
277 #define AWI_RXD_NEXT_LAST 0x80000000
278
279
280 #define AWI_RXD_HOST_DESC_STATE 0x9
281
282 #define AWI_RXD_ST_OWN 0x80 /* host owns this */
283 #define AWI_RXD_ST_CONSUMED 0x40 /* host is done */
284 #define AWI_RXD_ST_LF 0x20 /* last frag */
285 #define AWI_RXD_ST_CRC 0x08 /* CRC error */
286 #define AWI_RXD_ST_OFLO 0x02 /* possible buffer overrun */
287 #define AWI_RXD_ST_RXERROR 0x01 /* this frame is borked; discard me */
288
289 #define AWI_RXD_RSSI 0xa /* 1 byte: radio strength indicator */
290 #define AWI_RXD_INDEX 0xb /* 1 byte: FH hop index or DS channel */
291 #define AWI_RXD_LOCALTIME 0xc /* 4 bytes: local time of RX */
292 #define AWI_RXD_START_FRAME 0x10 /* 4 bytes: ptr to first received byte */
293 #define AWI_RXD_LEN 0x14 /* 2 bytes: rx len in bytes */
294 #define AWI_RXD_RATE 0x16 /* 1 byte: rx rate in 1e5 bps */
295
296 /*
297 * Transmit descriptors.
298 */
299
300 #define AWI_TXD_SIZE 0x18
301
302 #define AWI_TXD_START 0x00 /* pointer to start of frame */
303 #define AWI_TXD_NEXT 0x04 /* pointer to next TXD */
304 #define AWI_TXD_LENGTH 0x08 /* length of frame */
305 #define AWI_TXD_STATE 0x0a /* state */
306
307 #define AWI_TXD_ST_OWN 0x80 /* MAC owns this */
308 #define AWI_TXD_ST_DONE 0x40 /* MAC is done */
309 #define AWI_TXD_ST_REJ 0x20 /* MAC doesn't like */
310 #define AWI_TXD_ST_MSDU 0x10 /* MSDU timeout */
311 #define AWI_TXD_ST_ABRT 0x08 /* TX aborted */
312 #define AWI_TXD_ST_RETURNED 0x04 /* TX returned */
313 #define AWI_TXD_ST_RETRY 0x02 /* TX retries exceeded */
314 #define AWI_TXD_ST_ERROR 0x01 /* TX error */
315
316 #define AWI_TXD_RATE 0x0b /* rate */
317
318 #define AWI_RATE_1MBIT 10
319 #define AWI_RATE_2MBIT 20
320
321 #define AWI_TXD_NDA 0x0c /* num DIFS attempts */
322 #define AWI_TXD_NDF 0x0d /* num DIFS failures */
323 #define AWI_TXD_NSA 0x0e /* num SIFS attempts */
324 #define AWI_TXD_NSF 0x0f /* num SIFS failures */
325
326 #define AWI_TXD_NRA 0x14 /* num RTS attempts */
327 #define AWI_TXD_NDTA 0x15 /* num data attempts */
328 #define AWI_TXD_CTL 0x16 /* control */
329
330 #define AWI_TXD_CTL_PSN 0x80 /* preserve sequence in MAC frame */
331 #define AWI_TXD_CTL_BURST 0x02 /* host is doing 802.11 fragmt. */
332 #define AWI_TXD_CTL_FRAGS 0x01 /* override normal fragmentation */
333
334 /*
335 * MIB structures.
336 */
337
338 #define AWI_ESS_ID_SIZE (IEEE80211_NWID_LEN+2)
339 struct awi_mib_local {
340 u_int8_t Fragmentation_Dis;
341 u_int8_t Add_PLCP_Dis;
342 u_int8_t MAC_Hdr_Prsv;
343 u_int8_t Rx_Mgmt_Que_En;
344 u_int8_t Re_Assembly_Dis;
345 u_int8_t Strip_PLCP_Dis;
346 u_int8_t Rx_Error_Dis;
347 u_int8_t Power_Saving_Mode_Dis;
348 u_int8_t Accept_All_Multicast_Dis;
349 u_int8_t Check_Seq_Cntl_Dis;
350 u_int8_t Flush_CFP_Queue_On_CF_End;
351 u_int8_t Network_Mode;
352 u_int8_t PWD_Lvl;
353 u_int8_t CFP_Mode;
354 u_int8_t Tx_Buffer_Offset[4];
355 u_int8_t Tx_Buffer_Size[4];
356 u_int8_t Rx_Buffer_Offset[4];
357 u_int8_t Rx_Buffer_Size[4];
358 u_int8_t Acting_as_AP;
359 u_int8_t Fill_CFP;
360 };
361
362 struct awi_mib_mac {
363 u_int8_t _Reserved1[2];
364 u_int8_t _Reserved2[2];
365 u_int8_t aRTS_Threshold[2];
366 u_int8_t aCW_max[2];
367 u_int8_t aCW_min[2];
368 u_int8_t aPromiscuous_Enable;
369 u_int8_t _Reserved3;
370 u_int8_t _Reserved4[4];
371 u_int8_t aShort_Retry_Limit;
372 u_int8_t aLong_Retry_Limit;
373 u_int8_t aMax_Frame_Length[2];
374 u_int8_t aFragmentation_Threshold[2];
375 u_int8_t aProbe_Delay[2];
376 u_int8_t aMin_Probe_Response_Time[2];
377 u_int8_t aMax_Probe_Response_Time[2];
378 u_int8_t aMax_Transmit_MSDU_Lifetime[4];
379 u_int8_t aMax_Receive_MSDU_Lifetime[4];
380 u_int8_t aStation_Basic_Rate[2];
381 u_int8_t aDesired_ESS_ID[AWI_ESS_ID_SIZE];
382 };
383
384 struct awi_mib_stat {
385 u_int8_t aTransmitted_MPDU_Count[4];
386 u_int8_t aTransmitted_MSDU_Count[4];
387 u_int8_t aOctets_Transmitted_Cnt[4];
388 u_int8_t aMulticast_Transmitted_Frame_Count[2];
389 u_int8_t aBroadcast_Transmitted_Frame_Count[2];
390 u_int8_t aFailed_Count[4];
391 u_int8_t aRetry_Count[4];
392 u_int8_t aMultiple_Retry_Count[4];
393 u_int8_t aFrame_Duplicate_Count[4];
394 u_int8_t aRTS_Success_Count[4];
395 u_int8_t aRTS_Failure_Count[4];
396 u_int8_t aACK_Failure_Count[4];
397 u_int8_t aReceived_Frame_Count [4];
398 u_int8_t aOctets_Received_Count[4];
399 u_int8_t aMulticast_Received_Count[2];
400 u_int8_t aBroadcast_Received_Count[2];
401 u_int8_t aFCS_Error_Count[4];
402 u_int8_t aError_Count[4];
403 u_int8_t aWEP_Undecryptable_Count[4];
404 };
405
406 struct awi_mib_mgt {
407 u_int8_t aPower_Mgt_Mode;
408 u_int8_t aScan_Mode;
409 #define AWI_SCAN_PASSIVE 0x00
410 #define AWI_SCAN_ACTIVE 0x01
411 #define AWI_SCAN_BACKGROUND 0x02
412 u_int8_t aScan_State;
413 u_int8_t aDTIM_Period;
414 u_int8_t aATIM_Window[2];
415 u_int8_t Wep_Required;
416 u_int8_t _Reserved1;
417 u_int8_t aBeacon_Period[2];
418 u_int8_t aPassive_Scan_Duration[2];
419 u_int8_t aListen_Interval[2];
420 u_int8_t aMedium_Occupancy_Limit[2];
421 u_int8_t aMax_MPDU_Time[2];
422 u_int8_t aCFP_Max_Duration[2];
423 u_int8_t aCFP_Rate;
424 u_int8_t Do_Not_Receive_DTIMs;
425 u_int8_t aStation_ID[2];
426 u_int8_t aCurrent_BSS_ID[ETHER_ADDR_LEN];
427 u_int8_t aCurrent_ESS_ID[AWI_ESS_ID_SIZE];
428 };
429
430 #define AWI_GROUP_ADDR_SIZE 4
431 struct awi_mib_addr {
432 u_int8_t aMAC_Address[ETHER_ADDR_LEN];
433 u_int8_t aGroup_Addresses[AWI_GROUP_ADDR_SIZE][ETHER_ADDR_LEN];
434 u_int8_t aTransmit_Enable_Status;
435 u_int8_t _Reserved1;
436 };
437
438 #define AWI_PWR_LEVEL_SIZE 4
439 struct awi_mib_phy {
440 u_int8_t aSlot_Time[2];
441 u_int8_t aSIFS[2];
442 u_int8_t aMPDU_Maximum[2];
443 u_int8_t aHop_Time[2];
444 u_int8_t aSuprt_Data_Rates[4];
445 u_int8_t aCurrent_Reg_Domain;
446 #define AWI_REG_DOMAIN_US 0x10
447 #define AWI_REG_DOMAIN_CA 0x20
448 #define AWI_REG_DOMAIN_EU 0x30
449 #define AWI_REG_DOMAIN_ES 0x31
450 #define AWI_REG_DOMAIN_FR 0x32
451 #define AWI_REG_DOMAIN_JP 0x40
452 u_int8_t aPreamble_Lngth;
453 u_int8_t aPLCP_Hdr_Lngth;
454 u_int8_t Pwr_Up_Time[AWI_PWR_LEVEL_SIZE][2];
455 u_int8_t IEEE_PHY_Type;
456 #define AWI_PHY_TYPE_FH 1
457 #define AWI_PHY_TYPE_DS 2
458 #define AWI_PHY_TYPE_IR 3
459 u_int8_t RCR_33A_Bits[8];
460 };