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24 #ifndef _AR5K_AR5211_VAR_H
25 #define _AR5K_AR5211_VAR_H
26
27 #include <dev/ic/ar5xxx.h>
28
29
30
31
32
33 #define AR5K_AR5211_MAGIC 0x0000145b
34 #define AR5K_AR5211_TX_NUM_QUEUES 10
35
36 #if BYTE_ORDER == BIG_ENDIAN
37 #define AR5K_AR5211_INIT_CFG ( \
38 AR5K_AR5211_CFG_SWTD | AR5K_AR5211_CFG_SWRD \
39 )
40 #else
41 #define AR5K_AR5211_INIT_CFG 0x00000000
42 #endif
43
44
45
46
47
48
49 struct ar5k_ar5211_rx_desc {
50
51
52
53 u_int32_t rx_control_0;
54
55 #define AR5K_AR5211_DESC_RX_CTL0 0x00000000
56
57
58
59
60 u_int32_t rx_control_1;
61
62 #define AR5K_AR5211_DESC_RX_CTL1_BUF_LEN 0x00000fff
63 #define AR5K_AR5211_DESC_RX_CTL1_INTREQ 0x00002000
64 } __packed;
65
66 struct ar5k_ar5211_rx_status {
67
68
69
70 u_int32_t rx_status_0;
71
72 #define AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN 0x00000fff
73 #define AR5K_AR5211_DESC_RX_STATUS0_MORE 0x00001000
74 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000
75 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE_S 15
76 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000
77 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19
78 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x38000000
79 #define AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA_S 27
80
81
82
83
84 u_int32_t rx_status_1;
85
86 #define AR5K_AR5211_DESC_RX_STATUS1_DONE 0x00000001
87 #define AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002
88 #define AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR 0x00000004
89 #define AR5K_AR5211_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008
90 #define AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010
91 #define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR 0x000000e0
92 #define AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR_S 5
93 #define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100
94 #define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX 0x00007e00
95 #define AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_S 9
96 #define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
97 #define AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15
98 #define AR5K_AR5211_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000
99 } __packed;
100
101 #define AR5K_AR5211_DESC_RX_PHY_ERROR_NONE 0x00
102 #define AR5K_AR5211_DESC_RX_PHY_ERROR_TIMING 0x20
103 #define AR5K_AR5211_DESC_RX_PHY_ERROR_PARITY 0x40
104 #define AR5K_AR5211_DESC_RX_PHY_ERROR_RATE 0x60
105 #define AR5K_AR5211_DESC_RX_PHY_ERROR_LENGTH 0x80
106 #define AR5K_AR5211_DESC_RX_PHY_ERROR_64QAM 0xa0
107 #define AR5K_AR5211_DESC_RX_PHY_ERROR_SERVICE 0xc0
108 #define AR5K_AR5211_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
109
110 struct ar5k_ar5211_tx_desc {
111
112
113
114 u_int32_t tx_control_0;
115
116 #define AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN 0x00000fff
117 #define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE 0x003c0000
118 #define AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE_S 18
119 #define AR5K_AR5211_DESC_TX_CTL0_RTSENA 0x00400000
120 #define AR5K_AR5211_DESC_TX_CTL0_VEOL 0x00800000
121 #define AR5K_AR5211_DESC_TX_CTL0_CLRDMASK 0x01000000
122 #define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT 0x1e000000
123 #define AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT_S 25
124 #define AR5K_AR5211_DESC_TX_CTL0_INTREQ 0x20000000
125 #define AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000
126
127
128
129
130 u_int32_t tx_control_1;
131
132 #define AR5K_AR5211_DESC_TX_CTL1_BUF_LEN 0x00000fff
133 #define AR5K_AR5211_DESC_TX_CTL1_MORE 0x00001000
134 #define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
135 #define AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13
136 #define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE 0x00700000
137 #define AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE_S 20
138 #define AR5K_AR5211_DESC_TX_CTL1_NOACK 0x00800000
139 } __packed;
140
141 struct ar5k_ar5211_tx_status {
142
143
144
145 u_int32_t tx_status_0;
146
147 #define AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
148 #define AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
149 #define AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
150 #define AR5K_AR5211_DESC_TX_STATUS0_FILTERED 0x00000008
151 #define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0
152 #define AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4
153 #define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00
154 #define AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
155 #define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
156 #define AR5K_AR5211_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
157 #define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
158 #define AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
159
160
161
162
163 u_int32_t tx_status_1;
164
165 #define AR5K_AR5211_DESC_TX_STATUS1_DONE 0x00000001
166 #define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
167 #define AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM_S 1
168 #define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
169 #define AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
170 } __packed;
171
172
173
174
175 extern ar5k_attach_t ar5k_ar5211_attach;
176
177
178
179
180
181
182 #define AR5K_AR5211_INI { \
183 { 0x000c, 0x00000000 }, \
184 { 0x0028, 0x84849c9c }, \
185 { 0x002c, 0x7c7c7c7c }, \
186 { 0x0034, 0x00000005 }, \
187 { 0x0040, 0x00000000 }, \
188 { 0x0044, 0x00000008 }, \
189 { 0x0048, 0x00000008 }, \
190 { 0x004c, 0x00000010 }, \
191 { 0x0050, 0x00000000 }, \
192 { 0x0054, 0x0000001f }, \
193 { 0x0800, 0x00000000 }, \
194 { 0x0804, 0x00000000 }, \
195 { 0x0808, 0x00000000 }, \
196 { 0x080c, 0x00000000 }, \
197 { 0x0810, 0x00000000 }, \
198 { 0x0814, 0x00000000 }, \
199 { 0x0818, 0x00000000 }, \
200 { 0x081c, 0x00000000 }, \
201 { 0x0820, 0x00000000 }, \
202 { 0x0824, 0x00000000 }, \
203 { 0x1230, 0x00000000 }, \
204 { 0x8004, 0x00000000 }, \
205 { 0x8008, 0x00000000 }, \
206 { 0x800c, 0x00000000 }, \
207 { 0x8018, 0x00000000 }, \
208 { 0x8024, 0x00000000 }, \
209 { 0x8028, 0x00000030 }, \
210 { 0x802c, 0x0007ffff }, \
211 { 0x8030, 0x01ffffff }, \
212 { 0x8034, 0x00000031 }, \
213 { 0x8038, 0x00000000 }, \
214 { 0x803c, 0x00000000 }, \
215 { 0x8040, 0x00000000 }, \
216 { 0x8044, 0x00000002 }, \
217 { 0x8048, 0x00000000 }, \
218 { 0x8054, 0x00000000 }, \
219 { 0x8058, 0x00000000 }, \
220 \
221 { 0x9808, 0x00000000 }, \
222 { 0x980c, 0x2d849093 }, \
223 { 0x9810, 0x7d32e000 }, \
224 { 0x9814, 0x00000f6b }, \
225 { 0x981c, 0x00000000 }, \
226 { 0x982c, 0x00026ffe }, \
227 { 0x9830, 0x00000000 }, \
228 { 0x983c, 0x00020100 }, \
229 { 0x9840, 0x206a017a }, \
230 { 0x984c, 0x1284613c }, \
231 { 0x9854, 0x00000859 }, \
232 { 0x9868, 0x409a4190 }, \
233 { 0x986c, 0x050cb081 }, \
234 { 0x9870, 0x0000000f }, \
235 { 0x9874, 0x00000080 }, \
236 { 0x9878, 0x0000000c }, \
237 { 0x9900, 0x00000000 }, \
238 { 0x9904, 0x00000000 }, \
239 { 0x9908, 0x00000000 }, \
240 { 0x990c, 0x00800000 }, \
241 { 0x9910, 0x00000001 }, \
242 { 0x991c, 0x0000092a }, \
243 { 0x9920, 0x00000000 }, \
244 { 0x9924, 0x00058a05 }, \
245 { 0x9928, 0x00000001 }, \
246 { 0x992c, 0x00000000 }, \
247 { 0x9930, 0x00000000 }, \
248 { 0x9934, 0x00000000 }, \
249 { 0x9938, 0x00000000 }, \
250 { 0x993c, 0x0000003f }, \
251 { 0x9940, 0x00000004 }, \
252 { 0x9948, 0x00000000 }, \
253 { 0x994c, 0x00000000 }, \
254 { 0x9950, 0x00000000 }, \
255 { 0x9954, 0x5d50f14c }, \
256 { 0x9958, 0x00000018 }, \
257 { 0x995c, 0x004b6a8e }, \
258 { 0xa184, 0x06ff05ff }, \
259 { 0xa188, 0x07ff07ff }, \
260 { 0xa18c, 0x08ff08ff }, \
261 { 0xa190, 0x09ff09ff }, \
262 { 0xa194, 0x0aff0aff }, \
263 { 0xa198, 0x0bff0bff }, \
264 { 0xa19c, 0x0cff0cff }, \
265 { 0xa1a0, 0x0dff0dff }, \
266 { 0xa1a4, 0x0fff0eff }, \
267 { 0xa1a8, 0x12ff12ff }, \
268 { 0xa1ac, 0x14ff13ff }, \
269 { 0xa1b0, 0x16ff15ff }, \
270 { 0xa1b4, 0x19ff17ff }, \
271 { 0xa1b8, 0x1bff1aff }, \
272 { 0xa1bc, 0x1eff1dff }, \
273 { 0xa1c0, 0x23ff20ff }, \
274 { 0xa1c4, 0x27ff25ff }, \
275 { 0xa1c8, 0x2cff29ff }, \
276 { 0xa1cc, 0x31ff2fff }, \
277 { 0xa1d0, 0x37ff34ff }, \
278 { 0xa1d4, 0x3aff3aff }, \
279 { 0xa1d8, 0x3aff3aff }, \
280 { 0xa1dc, 0x3aff3aff }, \
281 { 0xa1e0, 0x3aff3aff }, \
282 { 0xa1e4, 0x3aff3aff }, \
283 { 0xa1e8, 0x3aff3aff }, \
284 { 0xa1ec, 0x3aff3aff }, \
285 { 0xa1f0, 0x3aff3aff }, \
286 { 0xa1f4, 0x3aff3aff }, \
287 { 0xa1f8, 0x3aff3aff }, \
288 { 0xa1fc, 0x3aff3aff }, \
289 \
290 { 0x9b00, 0x00000000 }, \
291 { 0x9b04, 0x00000020 }, \
292 { 0x9b08, 0x00000010 }, \
293 { 0x9b0c, 0x00000030 }, \
294 { 0x9b10, 0x00000008 }, \
295 { 0x9b14, 0x00000028 }, \
296 { 0x9b18, 0x00000004 }, \
297 { 0x9b1c, 0x00000024 }, \
298 { 0x9b20, 0x00000014 }, \
299 { 0x9b24, 0x00000034 }, \
300 { 0x9b28, 0x0000000c }, \
301 { 0x9b2c, 0x0000002c }, \
302 { 0x9b30, 0x00000002 }, \
303 { 0x9b34, 0x00000022 }, \
304 { 0x9b38, 0x00000012 }, \
305 { 0x9b3c, 0x00000032 }, \
306 { 0x9b40, 0x0000000a }, \
307 { 0x9b44, 0x0000002a }, \
308 { 0x9b48, 0x00000006 }, \
309 { 0x9b4c, 0x00000026 }, \
310 { 0x9b50, 0x00000016 }, \
311 { 0x9b54, 0x00000036 }, \
312 { 0x9b58, 0x0000000e }, \
313 { 0x9b5c, 0x0000002e }, \
314 { 0x9b60, 0x00000001 }, \
315 { 0x9b64, 0x00000021 }, \
316 { 0x9b68, 0x00000011 }, \
317 { 0x9b6c, 0x00000031 }, \
318 { 0x9b70, 0x00000009 }, \
319 { 0x9b74, 0x00000029 }, \
320 { 0x9b78, 0x00000005 }, \
321 { 0x9b7c, 0x00000025 }, \
322 { 0x9b80, 0x00000015 }, \
323 { 0x9b84, 0x00000035 }, \
324 { 0x9b88, 0x0000000d }, \
325 { 0x9b8c, 0x0000002d }, \
326 { 0x9b90, 0x00000003 }, \
327 { 0x9b94, 0x00000023 }, \
328 { 0x9b98, 0x00000013 }, \
329 { 0x9b9c, 0x00000033 }, \
330 { 0x9ba0, 0x0000000b }, \
331 { 0x9ba4, 0x0000002b }, \
332 { 0x9ba8, 0x0000002b }, \
333 { 0x9bac, 0x0000002b }, \
334 { 0x9bb0, 0x0000002b }, \
335 { 0x9bb4, 0x0000002b }, \
336 { 0x9bb8, 0x0000002b }, \
337 { 0x9bbc, 0x0000002b }, \
338 { 0x9bc0, 0x0000002b }, \
339 { 0x9bc4, 0x0000002b }, \
340 { 0x9bc8, 0x0000002b }, \
341 { 0x9bcc, 0x0000002b }, \
342 { 0x9bd0, 0x0000002b }, \
343 { 0x9bd4, 0x0000002b }, \
344 { 0x9bd8, 0x0000002b }, \
345 { 0x9bdc, 0x0000002b }, \
346 { 0x9be0, 0x0000002b }, \
347 { 0x9be4, 0x0000002b }, \
348 { 0x9be8, 0x0000002b }, \
349 { 0x9bec, 0x0000002b }, \
350 { 0x9bf0, 0x0000002b }, \
351 { 0x9bf4, 0x0000002b }, \
352 { 0x9bf8, 0x00000002 }, \
353 { 0x9bfc, 0x00000016 }, \
354 \
355 { 0x98d4, 0x00000020 }, \
356 { 0x98d8, 0x00601068 }, \
357 }
358
359 struct ar5k_ar5211_ini_mode {
360 u_int16_t mode_register;
361 u_int32_t mode_value[4];
362 };
363
364 #define AR5K_AR5211_INI_MODE { \
365 { 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } }, \
366 { 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
367 { 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
368 { 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
369 { 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
370 { 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
371 { 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
372 { 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
373 { 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
374 { 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
375 { 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, \
376 { 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, \
377 { 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, \
378 { 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, \
379 { 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, \
380 { 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, \
381 { 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, \
382 { 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, \
383 { 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, \
384 { 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, \
385 { 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, \
386 { 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, \
387 { 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, \
388 { 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, \
389 { 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, \
390 { 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, \
391 { 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, \
392 { 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, \
393 { 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, \
394 { 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, \
395 { 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, \
396 { 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, \
397 { 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, \
398 { 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, \
399 { 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, \
400 }
401
402 struct ar5k_ar5211_ini_rf {
403 u_int16_t rf_register;
404 u_int32_t rf_value[2];
405 };
406
407 #define AR5K_AR5211_INI_RF { \
408 { 0x0000a204, { 0x00000000, 0x00000000 } }, \
409 { 0x0000a208, { 0x503e4646, 0x503e4646 } }, \
410 { 0x0000a20c, { 0x6480416c, 0x6480416c } }, \
411 { 0x0000a210, { 0x0199a003, 0x0199a003 } }, \
412 { 0x0000a214, { 0x044cd610, 0x044cd610 } }, \
413 { 0x0000a218, { 0x13800040, 0x13800040 } }, \
414 { 0x0000a21c, { 0x1be00060, 0x1be00060 } }, \
415 { 0x0000a220, { 0x0c53800a, 0x0c53800a } }, \
416 { 0x0000a224, { 0x0014df3b, 0x0014df3b } }, \
417 { 0x0000a228, { 0x000001b5, 0x000001b5 } }, \
418 { 0x0000a22c, { 0x00000020, 0x00000020 } }, \
419 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
420 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
421 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
422 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
423 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
424 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
425 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
426 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
427 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
428 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
429 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
430 { 0x0000989c, { 0x00380000, 0x00380000 } }, \
431 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
432 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
433 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
434 { 0x0000989c, { 0x000400f9, 0x000400f9 } }, \
435 { 0x000098d4, { 0x00000000, 0x00000004 } }, \
436 \
437 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
438 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
439 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
440 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
441 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
442 { 0x0000989c, { 0x10000000, 0x10000000 } }, \
443 { 0x0000989c, { 0x04000000, 0x04000000 } }, \
444 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
445 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
446 { 0x0000989c, { 0x00000000, 0x00000000 } }, \
447 { 0x0000989c, { 0x00000000, 0x0a000000 } }, \
448 { 0x0000989c, { 0x00380080, 0x02380080 } }, \
449 { 0x0000989c, { 0x00020006, 0x00000006 } }, \
450 { 0x0000989c, { 0x00000092, 0x00000092 } }, \
451 { 0x0000989c, { 0x000000a0, 0x000000a0 } }, \
452 { 0x0000989c, { 0x00040007, 0x00040007 } }, \
453 { 0x000098d4, { 0x0000001a, 0x0000001a } }, \
454 { 0x0000989c, { 0x00000048, 0x00000048 } }, \
455 { 0x0000989c, { 0x00000010, 0x00000010 } }, \
456 { 0x0000989c, { 0x00000008, 0x00000008 } }, \
457 { 0x0000989c, { 0x0000000f, 0x0000000f } }, \
458 { 0x0000989c, { 0x000000f2, 0x00000062 } }, \
459 { 0x0000989c, { 0x0000904f, 0x0000904c } }, \
460 { 0x0000989c, { 0x0000125a, 0x0000129a } }, \
461 { 0x000098cc, { 0x0000000e, 0x0000000f } }, \
462 }
463
464 #endif