1 /* $OpenBSD: ad1848reg.h,v 1.6 1999/03/08 22:54:33 jason Exp $ */
2 /* $NetBSD: ad1848reg.h,v 1.4 1997/05/07 20:23:53 augustss Exp $ */
3
4 /*
5 * Copyright (c) 1994 John Brezak
6 * Copyright (c) 1991-1993 Regents of the University of California.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the Computer Systems
20 * Engineering Group at Lawrence Berkeley Laboratory.
21 * 4. Neither the name of the University nor of the Laboratory may be used
22 * to endorse or promote products derived from this software without
23 * specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 */
38 /*
39 * Copyright (c) 1993 Analog Devices Inc. All rights reserved
40 */
41
42 /*
43 * Further documentation can be found at:
44 * http://www.cirrus.com/products/overviews/cs4231.html
45 * (the CS4231A is an augmented ad1848, additional registers, etc).
46 */
47
48 /* parent driver is primarily responsible for checking this */
49 #define AD1848_BASE_VALID(base) (((base) & 0x003) == 0)
50
51 /* AD1848 direct registers */
52 #define AD1848_IADDR 0x00
53 #define AD1848_IDATA 0x01
54 #define AD1848_STATUS 0x02
55 #define AD1848_PIO 0x03
56
57 /* Gain constants */
58 #define GAIN_0 0x00
59 #define GAIN_1_5 0x01
60 #define GAIN_3 0x02
61 #define GAIN_4_5 0x03
62 #define GAIN_6 0x04
63 #define GAIN_7_5 0x05
64 #define GAIN_9 0x06
65 #define GAIN_10_5 0x07
66 #define GAIN_12 0x08
67 #define GAIN_13_5 0x09
68 #define GAIN_15 0x0a
69 #define GAIN_16_5 0x0b
70 #define GAIN_18 0x0c
71 #define GAIN_19_5 0x0d
72 #define GAIN_21 0x0e
73 #define GAIN_22_5 0x0f
74
75 /* Attenuation constants */
76
77 #define ATTEN_0 0x00
78 #define ATTEN_1_5 0x01
79 #define ATTEN_3 0x02
80 #define ATTEN_4_5 0x03
81 #define ATTEN_6 0x04
82 #define ATTEN_7_5 0x05
83 #define ATTEN_9 0x06
84 #define ATTEN_10_5 0x07
85 #define ATTEN_12 0x08
86 #define ATTEN_13_5 0x09
87 #define ATTEN_15 0x0a
88 #define ATTEN_16_5 0x0b
89 #define ATTEN_18 0x0c
90 #define ATTEN_19_5 0x0d
91 #define ATTEN_21 0x0e
92 #define ATTEN_22_5 0x0f
93
94 /* AD1848 Sound Port bit defines */
95 #define SP_IN_INIT 0x80
96 #define MODE_CHANGE_ENABLE 0x40
97 #define TRANSFER_DISABLE 0x20
98 #define ADDRESS_MASK 0xe0
99
100 /* Status bits */
101 #define INTERRUPT_STATUS 0x01
102 #define PLAYBACK_READY 0x02
103 #define PLAYBACK_LEFT 0x04
104 /* pbright is not left */
105 #define PLAYBACK_UPPER 0x08
106 /* bplower is not upper */
107 #define SAMPLE_ERROR 0x10
108 #define CAPTURE_READY 0x20
109 #define CAPTURE_LEFT 0x40
110 /* cpright is not left */
111 #define CAPTURE_UPPER 0x80
112 /* cplower is not upper */
113
114 /* Input & Output regs bits */
115 #define LINE_INPUT 0x00
116 #define AUX_INPUT 0x40
117 #define MIC_INPUT 0x80
118 #define MIXED_DAC_INPUT 0xc0
119 #define INPUT_GAIN_MASK 0xf0
120 #define INPUT_MIC_GAIN_ENABLE 0x20
121 #define INPUT_SOURCE_MASK 0x3f
122 #define AUX_INPUT_ATTEN_BITS 0x1f
123 #define AUX_INPUT_ATTEN_MASK 0xe0
124 #define AUX_INPUT_MUTE 0x80
125 #define OUTPUT_MUTE 0x80
126 #define OUTPUT_ATTEN_BITS 0x3f
127 #define OUTPUT_ATTEN_MASK 0xc0
128
129 /* Clock and Data format reg bits (some also Capture Data format) */
130 #define CLOCK_XTAL2 0x01
131 #define CLOCK_XTAL1 0x00
132 #define CLOCK_FREQ_MASK 0xf1
133 #define FMT_MONO 0x00
134 #define FMT_STEREO 0x10
135 #define FORMAT_MASK 0x1f
136 #define FMT_PCM8 0x00 /* 8-bit unsigned */
137 #define FMT_ULAW 0x20 /* 8-bit mu-law */
138 #define FMT_TWOS_COMP 0x40 /* 16-bit signed */
139 #define FMT_ALAW 0x60 /* 8-bit alaw */
140 #define FMT_ADPCM 0xa0 /* IMA ADPCM */
141 #define FMT_TWOS_COMP_BE 0xc0 /* 16-bit signed, big endian */
142
143 /* Interface Configuration reg bits */
144 #define PLAYBACK_ENABLE 0x01
145 #define CAPTURE_ENABLE 0x02
146 #define DUAL_DMA 0x00
147 #define SINGLE_DMA 0x04
148 #define AUTO_CAL_ENABLE 0x08
149 #define PLAYBACK_PIO_ENABLE 0x40
150 #define CAPTURE_PIO_ENABLE 0x80
151
152 /* Pin control bits */
153 #define INTERRUPT_ENABLE 0x02
154 #define XCTL0_ENABLE 0x40
155 #define XCTL1_ENABLE 0x80
156
157 /* Test and init reg bits */
158 #define OVERRANGE_LEFT_MASK 0xfc
159 #define OVERRANGE_RIGHT_MASK 0xf3
160 #define DATA_REQUEST_STATUS 0x10
161 #define AUTO_CAL_IN_PROG 0x20
162 #define PLAYBACK_UNDERRUN 0x40
163 #define CAPTURE_OVERRUN 0x80
164
165 /* Miscellaneous Control reg bits */
166 #define ID_MASK 0x70
167 #define MODE2 0x40
168
169 /* Digital Mix Control reg bits */
170 #define DIGITAL_MIX1_ENABLE 0x01
171 #define MIX_ATTEN_MASK 0xfc
172
173 /* AD1848 Sound Port reg defines */
174 #define SP_LEFT_INPUT_CONTROL 0x00
175 #define SP_RIGHT_INPUT_CONTROL 0x01
176 #define SP_LEFT_AUX1_CONTROL 0x02
177 #define SP_RIGHT_AUX1_CONTROL 0x03
178 #define SP_LEFT_AUX2_CONTROL 0x04
179 #define SP_RIGHT_AUX2_CONTROL 0x05
180 #define SP_LEFT_OUTPUT_CONTROL 0x06
181 #define SP_RIGHT_OUTPUT_CONTROL 0x07
182 #define SP_CLOCK_DATA_FORMAT 0x08
183 #define SP_INTERFACE_CONFIG 0x09
184 #define SP_PIN_CONTROL 0x0A
185 #define SP_TEST_AND_INIT 0x0B
186 #define SP_MISC_INFO 0x0C
187 #define SP_DIGITAL_MIX 0x0D
188 #define SP_UPPER_BASE_COUNT 0x0E
189 #define SP_LOWER_BASE_COUNT 0x0F
190