AD1848_IADDR      168 dev/isa/ad1848.c     ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
AD1848_IADDR      183 dev/isa/ad1848.c     ADWRITE(sc, AD1848_IADDR, (reg & 0xff) | sc->MCE_bit);
AD1848_IADDR      199 dev/isa/ad1848.c     ADWRITE(sc, AD1848_IADDR, sc->MCE_bit);
AD1848_IADDR      216 dev/isa/ad1848.c     while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
AD1848_IADDR      219 dev/isa/ad1848.c     if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
AD1848_IADDR      222 dev/isa/ad1848.c     ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);
AD1848_IADDR      224 dev/isa/ad1848.c     while (timeout > 0 && ADREAD(sc, AD1848_IADDR) != SP_TEST_AND_INIT)
AD1848_IADDR      227 dev/isa/ad1848.c     if (ADREAD(sc, AD1848_IADDR) == SP_TEST_AND_INIT)
AD1848_IADDR      324 dev/isa/ad1848.c     tmp = ADREAD(sc, AD1848_IADDR);
AD1848_IADDR      476 dev/isa/ad1848.c     while(ADREAD(sc, AD1848_IADDR) & SP_IN_INIT)
AD1848_IADDR      480 dev/isa/ad1848.c     ADWRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);
AD1848_IADDR      536 dev/isa/ad1848.c         while (timeout > 0 && ad_read(sc, AD1848_IADDR) & SP_IN_INIT)
AD1848_IADDR      547 dev/isa/ad1848.c 				   ad_read(sc, AD1848_IADDR) & SP_IN_INIT)
AD1848_IADDR     1270 dev/isa/ad1848.c 	while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
AD1848_IADDR     1285 dev/isa/ad1848.c     while (timeout > 0 && ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
AD1848_IADDR     1288 dev/isa/ad1848.c     if (ADREAD(sc, AD1848_IADDR) == SP_IN_INIT)
AD1848_IADDR     1322 dev/isa/ad1848.c 	    ADWRITE(sc, AD1848_IADDR, CS_IRQ_STATUS);
AD1848_IADDR      276 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, r);
AD1848_IADDR      286 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, r);
AD1848_IADDR      387 dev/sbus/cs4231.c 	     tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)
AD1848_IADDR      668 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE);
AD1848_IADDR      669 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_INTERFACE_CONFIG);
AD1848_IADDR      672 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | SP_CLOCK_DATA_FORMAT);
AD1848_IADDR      678 dev/sbus/cs4231.c 	     tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)
AD1848_IADDR      683 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);
AD1848_IADDR      688 dev/sbus/cs4231.c 	     tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)
AD1848_IADDR      693 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, 0);
AD1848_IADDR      695 dev/sbus/cs4231.c 	     tries && CS_READ(sc, AD1848_IADDR) == SP_IN_INIT; tries--)
AD1848_IADDR      700 dev/sbus/cs4231.c 	CS_WRITE(sc, AD1848_IADDR, SP_TEST_AND_INIT);