rdmsr 974 arch/i386/i386/est.c msr = rdmsr(MSR_PERF_STATUS);
rdmsr 1084 arch/i386/i386/est.c msr = rdmsr(MSR_PERF_CTL);
rdmsr 167 arch/i386/i386/i686_mem.c msrv = rdmsr(msr);
rdmsr 180 arch/i386/i386/i686_mem.c msrv = rdmsr(msr);
rdmsr 193 arch/i386/i386/i686_mem.c msrv = rdmsr(msr);
rdmsr 209 arch/i386/i386/i686_mem.c msrv = rdmsr(msr);
rdmsr 213 arch/i386/i386/i686_mem.c msrv = rdmsr(msr + 1);
rdmsr 292 arch/i386/i386/i686_mem.c wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800); /* disable MTRRs (E = 0) */
rdmsr 299 arch/i386/i386/i686_mem.c omsrv = rdmsr(msr);
rdmsr 311 arch/i386/i386/i686_mem.c omsrv = rdmsr(msr);
rdmsr 323 arch/i386/i386/i686_mem.c omsrv = rdmsr(msr);
rdmsr 338 arch/i386/i386/i686_mem.c omsrv = rdmsr(msr);
rdmsr 356 arch/i386/i386/i686_mem.c wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800); /* restore MTRR state */
rdmsr 538 arch/i386/i386/i686_mem.c mtrrcap = rdmsr(MSR_MTRRcap);
rdmsr 539 arch/i386/i386/i686_mem.c mtrrdef = rdmsr(MSR_MTRRdefType);
rdmsr 111 arch/i386/i386/k6_mem.c reg = rdmsr(UWCCR);
rdmsr 168 arch/i386/i386/k6_mem.c reg = rdmsr(UWCCR);
rdmsr 112 arch/i386/i386/longrun.c msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
rdmsr 117 arch/i386/i386/longrun.c msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
rdmsr 1048 arch/i386/i386/machdep.c if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
rdmsr 1125 arch/i386/i386/machdep.c msreg = rdmsr(0x110B);
rdmsr 1137 arch/i386/i386/machdep.c msreg = rdmsr(0x1107);
rdmsr 1150 arch/i386/i386/machdep.c msreg = rdmsr(0x1107);
rdmsr 1163 arch/i386/i386/machdep.c msreg = rdmsr(0x1107);
rdmsr 1176 arch/i386/i386/machdep.c msreg = rdmsr(0x1107);
rdmsr 1342 arch/i386/i386/machdep.c if (rdmsr(MSR_TEMPERATURE_TARGET) & MSR_TEMPERATURE_TARGET_LOW_BIT)
rdmsr 1345 arch/i386/i386/machdep.c msr = rdmsr(MSR_THERM_STATUS);
rdmsr 1390 arch/i386/i386/machdep.c if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))
rdmsr 1450 arch/i386/i386/machdep.c msr119 = rdmsr(MSR_BBL_CR_CTL);
rdmsr 1903 arch/i386/i386/machdep.c msr = rdmsr(MSR_EBL_CR_POWERON);
rdmsr 1928 arch/i386/i386/machdep.c msr = rdmsr(MSR_EBC_FREQUENCY_ID);
rdmsr 1980 arch/i386/i386/machdep.c msr = rdmsr(MSR_FSB_FREQ);
rdmsr 1997 arch/i386/i386/machdep.c msr = rdmsr(MSR_FSB_FREQ);
rdmsr 2032 arch/i386/i386/machdep.c msr = rdmsr(MSR_EBL_CR_POWERON);
rdmsr 2058 arch/i386/i386/machdep.c printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON));
rdmsr 2074 arch/i386/i386/machdep.c msr = rdmsr(MSR_EBC_FREQUENCY_ID);
rdmsr 2093 arch/i386/i386/machdep.c msr = rdmsr(MSR_EBL_CR_POWERON);
rdmsr 121 arch/i386/i386/p4tcc.c msreg = rdmsr(MSR_THERM_CONTROL);
rdmsr 126 arch/i386/i386/p4tcc.c vet = rdmsr(MSR_THERM_CONTROL);
rdmsr 107 arch/i386/i386/pctr.c msr11 = rdmsr(P5MSR_CTRSEL);
rdmsr 121 arch/i386/i386/pctr.c msr11 = rdmsr(P5MSR_CTRSEL);
rdmsr 126 arch/i386/i386/pctr.c st->pctr_hwc[0] = rdmsr(P5MSR_CTR0);
rdmsr 127 arch/i386/i386/pctr.c st->pctr_hwc[1] = rdmsr(P5MSR_CTR1);
rdmsr 157 arch/i386/i386/pctr.c st->pctr_fn[0] = rdmsr(P6MSR_CTRSEL0);
rdmsr 158 arch/i386/i386/pctr.c st->pctr_fn[1] = rdmsr(P6MSR_CTRSEL1);
rdmsr 170 arch/i386/i386/powernow-k7.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 180 arch/i386/i386/powernow-k7.c ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO;
rdmsr 202 arch/i386/i386/powernow-k7.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 336 arch/i386/i386/powernow-k7.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 413 arch/i386/i386/powernow-k7.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 160 arch/i386/i386/powernow-k8.c *status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 182 arch/i386/i386/powernow-k8.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 389 arch/i386/i386/powernow-k8.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 463 arch/i386/i386/powernow-k8.c status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
rdmsr 67 arch/i386/include/cpufunc.h static __inline u_int64_t rdmsr(u_int);
rdmsr 235 arch/i386/pci/glxsb.c msr = rdmsr(SB_GLD_MSR_CAP);
rdmsr 259 arch/i386/pci/glxsb.c msr = rdmsr(SB_GLD_MSR_CTRL);