outb 562 arch/i386/i386/cpu.c outb(IO_RTC, NVRAM_RESET); outb 563 arch/i386/i386/cpu.c outb(IO_RTC+1, NVRAM_RESET_JUMP); outb 611 arch/i386/i386/cpu.c outb(IO_RTC, NVRAM_RESET); outb 612 arch/i386/i386/cpu.c outb(IO_RTC+1, NVRAM_RESET_RST); outb 577 arch/i386/i386/ioapic.c outb(IMCR_ADDR, IMCR_REGISTER); outb 578 arch/i386/i386/ioapic.c outb(IMCR_DATA, IMCR_APIC); outb 348 arch/i386/i386/machdep.c outb(0x22, reg); outb 355 arch/i386/i386/machdep.c outb(0x22, reg); outb 356 arch/i386/i386/machdep.c outb(0x23, data); outb 3185 arch/i386/i386/machdep.c outb(IO_KBD + KBCMDP, KBC_PULSE0); outb 3187 arch/i386/i386/machdep.c outb(IO_KBD + KBCMDP, KBC_PULSE0); outb 308 arch/i386/include/bus.h outb((h) + (o), (v)); \ outb 51 arch/i386/include/i8259.h #define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8)) outb 93 arch/i386/include/i8259.h outb %al,$IO_ICU1 outb 97 arch/i386/include/i8259.h outb %al,$ICUADDR outb 104 arch/i386/include/i8259.h outb %al,$IO_ICU1 outb 112 arch/i386/include/i8259.h outb %al,$IO_ICU2 /* do the second ICU first */ ;\ outb 114 arch/i386/include/i8259.h outb %al,$IO_ICU1 outb 128 arch/i386/include/i8259.h outb %al,$(ICUADDR+1) outb 137 arch/i386/include/i8259.h outb %al,$(ICUADDR+1) ;\ outb 152 arch/i386/isa/clock.c outb(IO_RTC, reg); outb 166 arch/i386/isa/clock.c outb(IO_RTC, reg); outb 168 arch/i386/isa/clock.c outb(IO_RTC+1, datum); outb 208 arch/i386/isa/clock.c outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); outb 211 arch/i386/isa/clock.c outb(IO_TIMER1, TIMER_DIV(hz) % 256); outb 212 arch/i386/isa/clock.c outb(IO_TIMER1, TIMER_DIV(hz) / 256); outb 319 arch/i386/isa/clock.c outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); outb 705 arch/i386/isa/clock.c outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); outb 706 arch/i386/isa/clock.c outb(IO_TIMER1, tval & 0xff); outb 707 arch/i386/isa/clock.c outb(IO_TIMER1, tval >> 8); outb 731 arch/i386/isa/clock.c outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); outb 188 arch/i386/isa/isa_machdep.c outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ outb 189 arch/i386/isa/isa_machdep.c outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */ outb 190 arch/i386/isa/isa_machdep.c outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ outb 192 arch/i386/isa/isa_machdep.c outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ outb 194 arch/i386/isa/isa_machdep.c outb(IO_ICU1+1, 1); /* 8086 mode */ outb 196 arch/i386/isa/isa_machdep.c outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ outb 197 arch/i386/isa/isa_machdep.c outb(IO_ICU1, 0x68); /* special mask mode (if available) */ outb 198 arch/i386/isa/isa_machdep.c outb(IO_ICU1, 0x0a); /* Read IRR by default. */ outb 200 arch/i386/isa/isa_machdep.c outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ outb 203 arch/i386/isa/isa_machdep.c outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ outb 204 arch/i386/isa/isa_machdep.c outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ outb 205 arch/i386/isa/isa_machdep.c outb(IO_ICU2+1, IRQ_SLAVE); outb 207 arch/i386/isa/isa_machdep.c outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ outb 209 arch/i386/isa/isa_machdep.c outb(IO_ICU2+1, 1); /* 8086 mode */ outb 211 arch/i386/isa/isa_machdep.c outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ outb 212 arch/i386/isa/isa_machdep.c outb(IO_ICU2, 0x68); /* special mask mode (if available) */ outb 213 arch/i386/isa/isa_machdep.c outb(IO_ICU2, 0x0a); /* Read IRR by default. */ outb 102 arch/i386/isa/joy.c outb(port, 0xff); outb 170 arch/i386/isa/joy.c outb(IO_TIMER1 + TIMER_MODE, TIMER_SEL0); outb 66 arch/i386/isa/joy_isa.c outb(iobase, 0xff); outb 85 arch/i386/isa/joy_isa.c outb(iobase, 0xff); outb 74 arch/i386/isa/joy_isapnp.c outb(iobase, 0xff); outb 313 arch/i386/isa/npx.c outb(0xf1, 0); /* full reset on some systems, NOP on others */ outb 315 arch/i386/isa/npx.c outb(0xf0, 0); /* clear BUSY# latch */ outb 441 arch/i386/isa/npx.c outb(0xf0, 0); outb 183 arch/i386/pci/geodesc.c outb(0xCFC, 0x0F); outb 269 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); outb 270 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); outb 272 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, 0); outb 292 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); outb 293 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); outb 295 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, 0); outb 374 arch/i386/pci/pci_machdep.c outb(PCI_MODE1_ADDRESS_REG + 3, 0); outb 399 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_ENABLE_REG, 0); outb 400 arch/i386/pci/pci_machdep.c outb(PCI_MODE2_FORWARD_REG, 0); outb 57 arch/i386/stand/libsa/bioscons.c outb(IO_RTC, NVRAM_EQUIPMENT); outb 207 arch/i386/stand/libsa/bioscons.c outb(comports[minor(dev)] + com_cfcr, LCR_DLAB); outb 208 arch/i386/stand/libsa/bioscons.c outb(comports[minor(dev)] + com_dlbl, newsp); outb 209 arch/i386/stand/libsa/bioscons.c outb(comports[minor(dev)] + com_dlbh, newsp>>8); outb 210 arch/i386/stand/libsa/bioscons.c outb(comports[minor(dev)] + com_cfcr, LCR_8BITS); outb 68 arch/i386/stand/libsa/gateA20.c outb(0x92, data | 0x2); outb 71 arch/i386/stand/libsa/gateA20.c outb(0x92, data & ~0x2); outb 80 arch/i386/stand/libsa/gateA20.c outb(IO_KBD + KBCMDP, KBC_CMDWOUT); outb 84 arch/i386/stand/libsa/gateA20.c outb(IO_KBD + KBDATAP, KB_A20); outb 86 arch/i386/stand/libsa/gateA20.c outb(IO_KBD + KBDATAP, 0xcd); outb 173 dev/ic/pdqvar.h #define PDQ_OS_IOWR_8(t, base, offset, data) outb((base) + (offset), data) outb 261 dev/ic/pdqvar.h #define PDQ_OS_IOWR_8(port, data) outb(port, data) outb 282 dev/isa/aha.c outb(iobase + AHA_CTRL_PORT, AHA_CTRL_SRST); outb 285 dev/isa/aha.c outb(iobase + AHA_CMD_PORT, *ibuf++); outb 302 dev/isa/aha.c outb(iobase + AHA_CTRL_PORT, AHA_CTRL_SRST); outb 326 dev/isa/aha.c outb(iobase + AHA_CTRL_PORT, AHA_CTRL_IRST); outb 535 dev/isa/aha.c outb(iobase + AHA_CTRL_PORT, AHA_CTRL_IRST); outb 815 dev/isa/aha.c outb(iobase + AHA_CMD_PORT, AHA_START_SCSI); outb 935 dev/isa/aha.c outb(iobase + AHA_CTRL_PORT, AHA_CTRL_HRST | AHA_CTRL_SRST); outb 341 dev/isa/aria.c outb(0x204, 0x4c); outb 342 dev/isa/aria.c outb(0x205, 0x42); outb 343 dev/isa/aria.c outb(0x206, 0x00); outb 345 dev/isa/aria.c outb(0x201, 0x00); outb 347 dev/isa/aria.c outb(0x201, rba>>2); outb 365 dev/isa/aria.c outb(0x200, 0x0f); outb 368 dev/isa/aria.c outb(0x201, end|0x80); outb 391 dev/isa/aria.c outb(0x201, bits); outb 396 dev/isa/aria.c outb(0x200, func); outb 399 dev/isa/aria.c outb(0x201, (i&and) | or); outb 132 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_RESET); outb 134 dev/isa/if_el.c outb(iobase+EL_AC, 0); outb 139 dev/isa/if_el.c outb(iobase+EL_GPBL, i); outb 229 dev/isa/if_el.c outb(sc->sc_iobase+EL_AC, 0); outb 243 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_RESET); outb 245 dev/isa/if_el.c outb(iobase+EL_AC, 0); outb 248 dev/isa/if_el.c outb(iobase+i, sc->sc_arpcom.ac_enaddr[i]); outb 267 dev/isa/if_el.c outb(iobase+EL_RXC, EL_RXC_AGF | EL_RXC_DSHORT | EL_RXC_DDRIB | EL_RXC_DOFLOW | EL_RXC_PROMISC); outb 269 dev/isa/if_el.c outb(iobase+EL_RXC, EL_RXC_AGF | EL_RXC_DSHORT | EL_RXC_DDRIB | EL_RXC_DOFLOW | EL_RXC_ABROAD); outb 270 dev/isa/if_el.c outb(iobase+EL_RBC, 0); outb 274 dev/isa/if_el.c outb(iobase+EL_TXC, 0); outb 278 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_IRQE | EL_AC_RX); outb 332 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_HOST); outb 333 dev/isa/if_el.c outb(iobase+EL_RBC, 0); outb 338 dev/isa/if_el.c outb(iobase+EL_GPBL, off); outb 339 dev/isa/if_el.c outb(iobase+EL_GPBH, off >> 8); outb 346 dev/isa/if_el.c outb(iobase+EL_BUF, 0); outb 353 dev/isa/if_el.c outb(iobase+EL_GPBL, off); outb 354 dev/isa/if_el.c outb(iobase+EL_GPBH, off >> 8); outb 369 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_HOST); outb 386 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_IRQE | EL_AC_RX); outb 393 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_IRQE | EL_AC_RX); outb 417 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_TXFRX); outb 445 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_IRQE | EL_AC_RX); outb 460 dev/isa/if_el.c outb(iobase+EL_RXC, EL_RXC_AGF | EL_RXC_DSHORT | EL_RXC_DDRIB | EL_RXC_DOFLOW | EL_RXC_PROMISC); outb 462 dev/isa/if_el.c outb(iobase+EL_RXC, EL_RXC_AGF | EL_RXC_DSHORT | EL_RXC_DDRIB | EL_RXC_DOFLOW | EL_RXC_ABROAD); outb 464 dev/isa/if_el.c outb(iobase+EL_RBC, 0); outb 472 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_HOST); outb 485 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_IRQE | EL_AC_RX); outb 553 dev/isa/if_el.c outb(iobase+EL_GPBL, 0); outb 554 dev/isa/if_el.c outb(iobase+EL_GPBH, 0); outb 577 dev/isa/if_el.c outb(iobase+EL_RBC, 0); outb 578 dev/isa/if_el.c outb(iobase+EL_AC, EL_AC_RX); outb 486 dev/isa/if_ie.c outb(ELINK_ID_PORT, 0xff); outb 489 dev/isa/if_ie.c outb(PORT + IE507_CTRL, inb(PORT + IE507_CTRL) & 0xfc); /* XXX */ outb 502 dev/isa/if_ie.c outb(ELINK_ID_PORT, 0x00); outb 504 dev/isa/if_ie.c outb(ELINK_ID_PORT, 0x00); outb 507 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_NRST | EL_CTRL_BNK2); outb 535 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_NORMAL); outb 545 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_NRST); outb 554 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_NRST); outb 561 dev/isa/if_ie.c outb(PORT + IE507_ICTRL, 1); outb 591 dev/isa/if_ie.c outb(ia->ia_iobase + IEE16_ECTRL, IEE16_RESET_ASIC); outb 592 dev/isa/if_ie.c outb(ia->ia_iobase + IEE16_ECTRL, 0); outb 658 dev/isa/if_ie.c outb( PORT + IEE16_ECTRL, IEE16_RESET_586); outb 700 dev/isa/if_ie.c outb(PORT + IEE16_MEMDEC, decode & 0xFF); outb 702 dev/isa/if_ie.c outb(PORT + IEE16_MCTRL, adjust); outb 704 dev/isa/if_ie.c outb(PORT + IEE16_MPCTRL, (~decode & 0xFF)); outb 706 dev/isa/if_ie.c outb(PORT + IEE16_MECTRL, edecode); /*XXX disable Exxx */ outb 750 dev/isa/if_ie.c outb(PORT + IEE16_IRQ, sc->irq_encoded); outb 757 dev/isa/if_ie.c outb(PORT + IEE16_CONFIG, bart_config); outb 761 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, 0); outb 830 dev/isa/if_ie.c outb(PORT + IE507_ICTRL, 1); outb 834 dev/isa/if_ie.c outb(PORT + IEE16_IRQ, sc->irq_encoded); outb 881 dev/isa/if_ie.c outb(PORT + IE507_ICTRL, 1); outb 887 dev/isa/if_ie.c outb(PORT + IEE16_IRQ, sc->irq_encoded | IEE16_IRQ_ENABLE); outb 1635 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_RESET); outb 1637 dev/isa/if_ie.c outb(PORT + IE507_CTRL, EL_CTRL_NORMAL); outb 1646 dev/isa/if_ie.c outb(PORT + IEATT_RESET, 0); outb 1654 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, IEE16_RESET_586); outb 1656 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, 0); outb 1665 dev/isa/if_ie.c outb(PORT + IE507_ATTN, 1); outb 1673 dev/isa/if_ie.c outb(PORT + IEATT_ATTN, 0); outb 1680 dev/isa/if_ie.c outb(PORT + IEE16_ATTN, 0); outb 1693 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, ectrl); outb 1700 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, ectrl); outb 1720 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, ectrl); outb 1726 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, ectrl); outb 1762 dev/isa/if_ie.c outb(PORT + IEE16_ECTRL, ectrl); outb 1771 dev/isa/if_ie.c outb(PORT + IEE16_IRQ, sc->irq_encoded | IEE16_IRQ_ENABLE); outb 2100 dev/isa/if_ie.c outb(PORT + IEE16_CONFIG, bart_config); outb 199 dev/isa/opti.c outb( OPTI_PASSWD, opti_type ); outb 200 dev/isa/opti.c outb( port, byte ); outb 207 dev/isa/opti.c outb( OPTI_PASSWD, opti_type ); outb 161 dev/isa/pas.c #define paswrite(d, p) outb(p, d) outb 285 dev/isa/pas.c outb(MASTER_DECODE, 0xbc); outb 300 dev/isa/pas.c outb(MASTER_DECODE, iobase >> 2); outb 749 dev/isa/pss.c outb(WSS_BASE_ADDRESS+WSS_CONFIG, 0); outb 895 dev/isa/pss.c outb(sc->sc_iobase+WSS_CONFIG, (bits | 0x40)); outb 899 dev/isa/pss.c outb(sc->sc_iobase+WSS_CONFIG, (bits | wss_dma_bits[sc->sc_drq])); outb 383 dev/pci/gdt_pci.c outb(0x00,PTR2USHORT(&ha->plx->control1)); outb 384 dev/pci/gdt_pci.c outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); outb 392 dev/pci/gdt_pci.c outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); outb 422 dev/pci/gdt_pci.c outb(1,PTR2USHORT(&ha->plx->ldoor_reg));