VR_MIICMD         179 dev/pci/if_vr.c 	CSR_WRITE_1(sc, VR_MIICMD,			\
VR_MIICMD         180 dev/pci/if_vr.c 		CSR_READ_1(sc, VR_MIICMD) | (x))
VR_MIICMD         183 dev/pci/if_vr.c 	CSR_WRITE_1(sc, VR_MIICMD,			\
VR_MIICMD         184 dev/pci/if_vr.c 		CSR_READ_1(sc, VR_MIICMD) & ~(x))
VR_MIICMD         248 dev/pci/if_vr.c 	CSR_WRITE_1(sc, VR_MIICMD, 0);
VR_MIICMD         249 dev/pci/if_vr.c 	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
VR_MIICMD         278 dev/pci/if_vr.c 	ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
VR_MIICMD         300 dev/pci/if_vr.c 			if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
VR_MIICMD         333 dev/pci/if_vr.c 	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
VR_MIICMD         336 dev/pci/if_vr.c 		if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
VR_MIICMD         361 dev/pci/if_vr.c 	CSR_WRITE_1(sc, VR_MIICMD, 0);
VR_MIICMD         362 dev/pci/if_vr.c 	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
VR_MIICMD         415 dev/pci/if_vr.c 	VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
VR_MIICMD         418 dev/pci/if_vr.c 		if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
VR_MIICMD         715 dev/pci/if_vr.c 	VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);