VGE_CR1_TIMER0_ENABLE 1177 dev/pci/if_vge.c 		CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
VGE_CR1_TIMER0_ENABLE 1485 dev/pci/if_vge.c 	CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);