AR5K_REG_SM 577 dev/ic/ar5210.c AR5K_REG_SM(-1, AR5K_AR5210_PHY_SIG_FIRPWR)); AR5K_REG_SM 582 dev/ic/ar5210.c AR5K_REG_SM(-1, AR5K_AR5210_PHY_AGCCOARSE_HI) | AR5K_REG_SM 583 dev/ic/ar5210.c AR5K_REG_SM(-127, AR5K_AR5210_PHY_AGCCOARSE_LO)); AR5K_REG_SM 588 dev/ic/ar5210.c AR5K_REG_SM(2, AR5K_AR5210_PHY_ADCSAT_ICNT) | AR5K_REG_SM 589 dev/ic/ar5210.c AR5K_REG_SM(12, AR5K_AR5210_PHY_ADCSAT_THR)); AR5K_REG_SM 860 dev/ic/ar5210.c | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_AR5210_RETRY_LMT_SLG_RETRY) AR5K_REG_SM 861 dev/ic/ar5210.c | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_AR5210_RETRY_LMT_SSH_RETRY) AR5K_REG_SM 862 dev/ic/ar5210.c | AR5K_REG_SM(retry_lg, AR5K_AR5210_RETRY_LMT_LG_RETRY) AR5K_REG_SM 863 dev/ic/ar5210.c | AR5K_REG_SM(retry_sh, AR5K_AR5210_RETRY_LMT_SH_RETRY)); AR5K_REG_SM 1034 dev/ic/ar5210.c AR5K_REG_SM(frame_type, AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE); AR5K_REG_SM 1036 dev/ic/ar5210.c AR5K_REG_SM(tx_rate0, AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE); AR5K_REG_SM 1056 dev/ic/ar5210.c AR5K_REG_SM(key_index, AR5K_REG_SM 2112 dev/ic/ar5210.c AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_REG_SM 2114 dev/ic/ar5210.c AR5K_REG_SM(state->bs_interval, AR5K_AR5210_BEACON_PERIOD)); AR5K_REG_SM 923 dev/ic/ar5211.c AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_REG_SM 925 dev/ic/ar5211.c AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_REG_SM 927 dev/ic/ar5211.c AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | AR5K_REG_SM 928 dev/ic/ar5211.c AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); AR5K_REG_SM 945 dev/ic/ar5211.c AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | AR5K_REG_SM 946 dev/ic/ar5211.c AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | AR5K_REG_SM 947 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, AR5K_REG_SM 958 dev/ic/ar5211.c AR5K_REG_SM(tq->tqi_cbr_period, AR5K_REG_SM 960 dev/ic/ar5211.c AR5K_REG_SM(tq->tqi_cbr_overflow_limit, AR5K_REG_SM 971 dev/ic/ar5211.c AR5K_REG_SM(tq->tqi_ready_time, AR5K_REG_SM 978 dev/ic/ar5211.c AR5K_REG_SM(tq->tqi_burst_time, AR5K_REG_SM 1046 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | AR5K_REG_SM 1047 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); AR5K_REG_SM 1049 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); AR5K_REG_SM 1051 dev/ic/ar5211.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); AR5K_REG_SM 1151 dev/ic/ar5211.c AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | AR5K_REG_SM 1152 dev/ic/ar5211.c AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); AR5K_REG_SM 1154 dev/ic/ar5211.c AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); AR5K_REG_SM 1176 dev/ic/ar5211.c AR5K_REG_SM(key_index, AR5K_REG_SM 2211 dev/ic/ar5211.c AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_REG_SM 2212 dev/ic/ar5211.c AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, AR5K_REG_SM 905 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txpower.txp_max, AR5K_REG_SM 1082 dev/ic/ar5212.c AR5K_REG_SM(AR5K_INIT_SLG_RETRY, AR5K_REG_SM 1084 dev/ic/ar5212.c AR5K_REG_SM(AR5K_INIT_SSH_RETRY, AR5K_REG_SM 1086 dev/ic/ar5212.c AR5K_REG_SM(retry_lg, AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY) | AR5K_REG_SM 1087 dev/ic/ar5212.c AR5K_REG_SM(retry_sh, AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY)); AR5K_REG_SM 1104 dev/ic/ar5212.c AR5K_REG_SM(cw_min, AR5K_AR5212_DCU_LCL_IFS_CW_MIN) | AR5K_REG_SM 1105 dev/ic/ar5212.c AR5K_REG_SM(cw_max, AR5K_AR5212_DCU_LCL_IFS_CW_MAX) | AR5K_REG_SM 1106 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, AR5K_REG_SM 1117 dev/ic/ar5212.c AR5K_REG_SM(tq->tqi_cbr_period, AR5K_REG_SM 1119 dev/ic/ar5212.c AR5K_REG_SM(tq->tqi_cbr_overflow_limit, AR5K_REG_SM 1130 dev/ic/ar5212.c AR5K_REG_SM(tq->tqi_ready_time, AR5K_REG_SM 1137 dev/ic/ar5212.c AR5K_REG_SM(tq->tqi_burst_time, AR5K_REG_SM 1205 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXOK) | AR5K_REG_SM 1206 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR0_QCU_TXDESC)); AR5K_REG_SM 1208 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR1_QCU_TXERR)); AR5K_REG_SM 1210 dev/ic/ar5212.c AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5212_SIMR2_QCU_TXURN)); AR5K_REG_SM 1310 dev/ic/ar5212.c AR5K_REG_SM(tx_power, AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER) | AR5K_REG_SM 1311 dev/ic/ar5212.c AR5K_REG_SM(antenna_mode, AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT); AR5K_REG_SM 1313 dev/ic/ar5212.c AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE); AR5K_REG_SM 1315 dev/ic/ar5212.c AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES, AR5K_REG_SM 1341 dev/ic/ar5212.c AR5K_REG_SM(key_index, AR5K_REG_SM 1355 dev/ic/ar5212.c AR5K_REG_SM(rtscts_rate, AR5K_REG_SM 1401 dev/ic/ar5212.c AR5K_REG_SM(tx_tries##_n, \ AR5K_REG_SM 1404 dev/ic/ar5212.c AR5K_REG_SM(tx_rate##_n, \ AR5K_REG_SM 2551 dev/ic/ar5212.c AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, AR5K_REG_SM 2552 dev/ic/ar5212.c AR5K_AR5212_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, AR5K_REG_SM 2585 dev/ic/ar5212.c AR5K_REG_SM((state->bs_nextdtim - 3) << 3, AR5K_REG_SM 2587 dev/ic/ar5212.c AR5K_REG_SM(10, AR5K_AR5212_SLEEP0_CABTO) | AR5K_REG_SM 2591 dev/ic/ar5212.c AR5K_REG_SM((next_beacon - 3) << 3, AR5K_REG_SM 2593 dev/ic/ar5212.c AR5K_REG_SM(10, AR5K_AR5212_SLEEP1_BEACON_TO)); AR5K_REG_SM 2595 dev/ic/ar5212.c AR5K_REG_SM(interval, AR5K_AR5212_SLEEP2_TIM_PER) | AR5K_REG_SM 2596 dev/ic/ar5212.c AR5K_REG_SM(dtim, AR5K_AR5212_SLEEP2_DTIM_PER));