AR5K_REG_ENABLE_BITS 528 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGC, \ AR5K_REG_ENABLE_BITS 541 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_REG_ENABLE_BITS 631 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 653 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 718 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, HAL_INT_GLOBAL); AR5K_REG_ENABLE_BITS 1219 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_DIAG_SW, AR5K_AR5210_DIAG_SW_DIS_RX); AR5K_REG_ENABLE_BITS 1237 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL1, AR5K_REG_ENABLE_BITS 1240 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_MCAST_FIL0, AR5K_REG_ENABLE_BITS 1671 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_AR5210_IMR_GPIO); AR5K_REG_ENABLE_BITS 1690 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_BEACON, AR5K_REG_ENABLE_BITS 2018 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_STA_ID1, AR5K_REG_ENABLE_BITS 2305 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_IMR, AR5K_REG_ENABLE_BITS 2332 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); AR5K_REG_ENABLE_BITS 2360 dev/ic/ar5210.c AR5K_REG_ENABLE_BITS(AR5K_AR5210_PCICFG, AR5K_AR5210_PCICFG_EEAE); AR5K_REG_ENABLE_BITS 521 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, AR5K_REG_ENABLE_BITS 569 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, AR5K_REG_ENABLE_BITS 579 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); AR5K_REG_ENABLE_BITS 621 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 631 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, AR5K_REG_ENABLE_BITS 744 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, AR5K_REG_ENABLE_BITS 751 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 962 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 965 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 983 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1003 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1008 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), AR5K_REG_ENABLE_BITS 1022 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1027 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), AR5K_REG_ENABLE_BITS 1033 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1326 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); AR5K_REG_ENABLE_BITS 1344 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, AR5K_REG_ENABLE_BITS 1347 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, AR5K_REG_ENABLE_BITS 1657 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); AR5K_REG_ENABLE_BITS 1777 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); AR5K_REG_ENABLE_BITS 1797 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, AR5K_REG_ENABLE_BITS 2351 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, AR5K_REG_ENABLE_BITS 2435 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_REG_ENABLE_BITS 2467 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, AR5K_REG_ENABLE_BITS 2491 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, AR5K_REG_ENABLE_BITS 2493 dev/ic/ar5211.c AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, AR5K_REG_ENABLE_BITS 652 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG, AR5K_REG_ENABLE_BITS 701 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, AR5K_REG_ENABLE_BITS 717 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, s_led[0]); AR5K_REG_ENABLE_BITS 759 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 768 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, AR5K_REG_ENABLE_BITS 892 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_IQ, AR5K_REG_ENABLE_BITS 899 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PHY_AGCCTL, AR5K_REG_ENABLE_BITS 1121 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1124 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1142 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1162 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1167 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), AR5K_REG_ENABLE_BITS 1181 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1186 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_DCU_MISC(queue), AR5K_REG_ENABLE_BITS 1192 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_QCU_MISC(queue), AR5K_REG_ENABLE_BITS 1557 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_DIAG_SW, AR5K_AR5212_DIAG_SW_DIS_RX); AR5K_REG_ENABLE_BITS 1575 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL1, AR5K_REG_ENABLE_BITS 1578 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_MCAST_FIL0, AR5K_REG_ENABLE_BITS 1631 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_RXCFG, AR5K_REG_ENABLE_BITS 1939 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PCICFG, led); AR5K_REG_ENABLE_BITS 2072 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_AR5212_PIMR_GPIO); AR5K_REG_ENABLE_BITS 2092 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_BEACON, AR5K_REG_ENABLE_BITS 2528 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_STA_ID1, AR5K_REG_ENABLE_BITS 2725 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_SIMR2, AR5K_REG_ENABLE_BITS 2810 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_PIMR, AR5K_REG_ENABLE_BITS 2842 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, AR5K_REG_ENABLE_BITS 2866 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD, AR5K_REG_ENABLE_BITS 2868 dev/ic/ar5212.c AR5K_REG_ENABLE_BITS(AR5K_AR5212_EEPROM_CMD,