GG82563_REG      1986 dev/pci/if_em_hw.c         ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
GG82563_REG      1989 dev/pci/if_em_hw.c         ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
GG82563_REG      1993 dev/pci/if_em_hw.c         ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
GG82563_REG      2633 dev/pci/if_em_hw.h         GG82563_REG(0, 16) /* PHY Specific Control */
GG82563_REG      2635 dev/pci/if_em_hw.h         GG82563_REG(0, 17) /* PHY Specific Status */
GG82563_REG      2637 dev/pci/if_em_hw.h         GG82563_REG(0, 18) /* Interrupt Enable */
GG82563_REG      2639 dev/pci/if_em_hw.h         GG82563_REG(0, 19) /* PHY Specific Status 2 */
GG82563_REG      2641 dev/pci/if_em_hw.h         GG82563_REG(0, 21) /* Receive Error Counter */
GG82563_REG      2643 dev/pci/if_em_hw.h         GG82563_REG(0, 22) /* Page Select */
GG82563_REG      2645 dev/pci/if_em_hw.h         GG82563_REG(0, 26) /* PHY Specific Control 2 */
GG82563_REG      2647 dev/pci/if_em_hw.h         GG82563_REG(0, 29) /* Alternate Page Select */
GG82563_REG      2649 dev/pci/if_em_hw.h         GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
GG82563_REG      2652 dev/pci/if_em_hw.h         GG82563_REG(2, 21) /* MAC Specific Control Register */
GG82563_REG      2654 dev/pci/if_em_hw.h         GG82563_REG(2, 26) /* MAC Specific Control 2 */
GG82563_REG      2657 dev/pci/if_em_hw.h         GG82563_REG(5, 26) /* DSP Distance */
GG82563_REG      2661 dev/pci/if_em_hw.h         GG82563_REG(193, 16) /* Kumeran Mode Control */
GG82563_REG      2663 dev/pci/if_em_hw.h         GG82563_REG(193, 17) /* Port Reset */
GG82563_REG      2665 dev/pci/if_em_hw.h         GG82563_REG(193, 18) /* Revision ID */
GG82563_REG      2667 dev/pci/if_em_hw.h         GG82563_REG(193, 19) /* Device ID */
GG82563_REG      2669 dev/pci/if_em_hw.h         GG82563_REG(193, 20) /* Power Management Control */
GG82563_REG      2671 dev/pci/if_em_hw.h         GG82563_REG(193, 25) /* Rate Adaptation Control */
GG82563_REG      2675 dev/pci/if_em_hw.h         GG82563_REG(194, 16) /* FIFO's Control/Status */
GG82563_REG      2677 dev/pci/if_em_hw.h         GG82563_REG(194, 17) /* Control */
GG82563_REG      2679 dev/pci/if_em_hw.h         GG82563_REG(194, 18) /* Inband Control */
GG82563_REG      2681 dev/pci/if_em_hw.h         GG82563_REG(194, 19) /* Diagnostic */
GG82563_REG      2683 dev/pci/if_em_hw.h         GG82563_REG(194, 20) /* Acknowledge Timeouts */
GG82563_REG      2685 dev/pci/if_em_hw.h         GG82563_REG(194, 21) /* Advertised Ability */
GG82563_REG      2687 dev/pci/if_em_hw.h         GG82563_REG(194, 23) /* Link Partner Advertised Ability */
GG82563_REG      2689 dev/pci/if_em_hw.h         GG82563_REG(194, 24) /* Advertised Next Page */
GG82563_REG      2691 dev/pci/if_em_hw.h         GG82563_REG(194, 25) /* Link Partner Advertised Next page */
GG82563_REG      2693 dev/pci/if_em_hw.h         GG82563_REG(194, 26) /* Misc. */