_reg             1362 dev/ic/ar5xxx.h #define AR5K_REG_WRITE(_reg, _val)					\
_reg             1363 dev/ic/ar5xxx.h 	bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val))
_reg             1364 dev/ic/ar5xxx.h #define AR5K_REG_READ(_reg)						\
_reg             1365 dev/ic/ar5xxx.h 	bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))
_reg             1371 dev/ic/ar5xxx.h #define AR5K_REG_WRITE_BITS(_reg, _flags, _val)				\
_reg             1372 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) |	\
_reg             1374 dev/ic/ar5xxx.h #define AR5K_REG_MASKED_BITS(_reg, _flags, _mask)			\
_reg             1375 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
_reg             1376 dev/ic/ar5xxx.h #define AR5K_REG_ENABLE_BITS(_reg, _flags)				\
_reg             1377 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
_reg             1378 dev/ic/ar5xxx.h #define AR5K_REG_DISABLE_BITS(_reg, _flags)				\
_reg             1379 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
_reg             1381 dev/ic/ar5xxx.h #define AR5K_PHY_WRITE(_reg, _val)					\
_reg             1382 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
_reg             1383 dev/ic/ar5xxx.h #define AR5K_PHY_READ(_reg)						\
_reg             1384 dev/ic/ar5xxx.h 	AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
_reg             1399 dev/ic/ar5xxx.h #define AR5K_REG_READ_Q(_reg, _queue)					\
_reg             1400 dev/ic/ar5xxx.h 	(AR5K_REG_READ(_reg) & (1 << _queue))				\
_reg             1402 dev/ic/ar5xxx.h #define AR5K_REG_WRITE_Q(_reg, _queue)					\
_reg             1403 dev/ic/ar5xxx.h 	AR5K_REG_WRITE(_reg, (1 << _queue))
_reg             1405 dev/ic/ar5xxx.h #define AR5K_Q_ENABLE_BITS(_reg, _queue) do {				\
_reg             1406 dev/ic/ar5xxx.h 	_reg |= 1 << _queue;						\
_reg             1409 dev/ic/ar5xxx.h #define AR5K_Q_DISABLE_BITS(_reg, _queue) do {				\
_reg             1410 dev/ic/ar5xxx.h 	_reg &= ~(1 << _queue);						\