xilinx 401 dev/pci/if_san_common.h sdla_xilinx_t xilinx;
xilinx 312 dev/pci/if_san_xilinx.c card->u.xilinx.num_of_ch = 0;
xilinx 313 dev/pci/if_san_xilinx.c card->u.xilinx.mru_trans = 1500;
xilinx 314 dev/pci/if_san_xilinx.c card->u.xilinx.dma_per_ch = 10;
xilinx 339 dev/pci/if_san_xilinx.c sdla_getcfg(card->hw, SDLA_BASEADDR, &card->u.xilinx.bar);
xilinx 343 dev/pci/if_san_xilinx.c timeout_set(&card->u.xilinx.led_timer, aft_led_timer, (void *)card);
xilinx 495 dev/pci/if_san_xilinx.c card->devname, card->u.xilinx.dma_per_ch, sc->dma_mtu);
xilinx 497 dev/pci/if_san_xilinx.c if (aft_alloc_rx_dma_buff(sc, card->u.xilinx.dma_per_ch) == 0)
xilinx 556 dev/pci/if_san_xilinx.c timeout_del(&card->u.xilinx.led_timer);
xilinx 971 dev/pci/if_san_xilinx.c card->u.xilinx.num_of_time_slots = NUM_OF_T1_CHANNELS;
xilinx 975 dev/pci/if_san_xilinx.c card->u.xilinx.num_of_time_slots = NUM_OF_E1_CHANNELS;
xilinx 1228 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 1245 dev/pci/if_san_xilinx.c &card->u.xilinx.time_slot_map, i)) {
xilinx 1269 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 1272 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)&card->u.xilinx.time_slot_map, i);
xilinx 1312 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 1314 dev/pci/if_san_xilinx.c &card->u.xilinx.time_slot_map, i)) {
xilinx 1434 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 1468 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++)
xilinx 1477 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++)
xilinx 1480 dev/pci/if_san_xilinx.c &card->u.xilinx.time_slot_map, i);
xilinx 1598 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)&card->u.xilinx.active_ch_map, sc->logic_ch_num);
xilinx 1615 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)&card->u.xilinx.active_ch_map, sc->logic_ch_num);
xilinx 2300 dev/pci/if_san_xilinx.c sc->if_name, card->u.xilinx.num_of_time_slots,
xilinx 2301 dev/pci/if_san_xilinx.c card->u.xilinx.logic_ch_map, __FUNCTION__, __LINE__);
xilinx 2308 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2309 dev/pci/if_san_xilinx.c if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) {
xilinx 2310 dev/pci/if_san_xilinx.c bit_set((u_int8_t *)&card->u.xilinx.logic_ch_map, i);
xilinx 2319 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2320 dev/pci/if_san_xilinx.c if (!bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map, i)) {
xilinx 2326 dev/pci/if_san_xilinx.c if (card->u.xilinx.dev_to_ch_map[(unsigned char)logic_ch]) {
xilinx 2334 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[(unsigned char)logic_ch] = (void *)sc;
xilinx 2336 dev/pci/if_san_xilinx.c if (logic_ch > card->u.xilinx.top_logic_ch) {
xilinx 2337 dev/pci/if_san_xilinx.c card->u.xilinx.top_logic_ch = logic_ch;
xilinx 2347 dev/pci/if_san_xilinx.c bit_clear((u_int8_t *)&card->u.xilinx.logic_ch_map, logic_ch);
xilinx 2348 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[logic_ch] = NULL;
xilinx 2350 dev/pci/if_san_xilinx.c if (logic_ch >= card->u.xilinx.top_logic_ch) {
xilinx 2353 dev/pci/if_san_xilinx.c card->u.xilinx.top_logic_ch = XILINX_DEFLT_ACTIVE_CH;
xilinx 2355 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2356 dev/pci/if_san_xilinx.c if (card->u.xilinx.dev_to_ch_map[logic_ch])
xilinx 2357 dev/pci/if_san_xilinx.c card->u.xilinx.top_logic_ch = i;
xilinx 2379 dev/pci/if_san_xilinx.c reg |= (card->u.xilinx.top_logic_ch << DMA_ACTIVE_CHANNEL_BIT_SHIFT);
xilinx 2581 dev/pci/if_san_xilinx.c tx_status &= card->u.xilinx.active_ch_map;
xilinx 2582 dev/pci/if_san_xilinx.c rx_status &= card->u.xilinx.active_ch_map;
xilinx 2585 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2587 dev/pci/if_san_xilinx.c bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map,
xilinx 2592 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[i];
xilinx 2632 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2634 dev/pci/if_san_xilinx.c bit_test((u_int8_t *)&card->u.xilinx.logic_ch_map,
xilinx 2638 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[i];
xilinx 2752 dev/pci/if_san_xilinx.c if (card->u.xilinx.state_change_exit_isr) {
xilinx 2753 dev/pci/if_san_xilinx.c card->u.xilinx.state_change_exit_isr = 0;
xilinx 2784 dev/pci/if_san_xilinx.c dma_rx_reg &= card->u.xilinx.active_ch_map;
xilinx 2789 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2792 dev/pci/if_san_xilinx.c &card->u.xilinx.logic_ch_map, i)) {
xilinx 2794 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[i];
xilinx 2811 dev/pci/if_san_xilinx.c dma_tx_reg &= card->u.xilinx.active_ch_map;
xilinx 2816 dev/pci/if_san_xilinx.c for (i = 0; i < card->u.xilinx.num_of_time_slots; i++) {
xilinx 2819 dev/pci/if_san_xilinx.c &card->u.xilinx.logic_ch_map, i)) {
xilinx 2821 dev/pci/if_san_xilinx.c card->u.xilinx.dev_to_ch_map[i];
xilinx 2904 dev/pci/if_san_xilinx.c card->u.xilinx.state_change_exit_isr = 1;
xilinx 2908 dev/pci/if_san_xilinx.c card->u.xilinx.state_change_exit_isr = 1;
xilinx 3253 dev/pci/if_san_xilinx.c timeslot = card->u.xilinx.num_of_time_slots - 2;
xilinx 3255 dev/pci/if_san_xilinx.c timeslot = card->u.xilinx.num_of_time_slots - 1;
xilinx 3418 dev/pci/if_san_xilinx.c card->devname, reg, card->u.xilinx.fifo_addr_map);
xilinx 3421 dev/pci/if_san_xilinx.c if (card->u.xilinx.fifo_addr_map & (reg << i))
xilinx 3423 dev/pci/if_san_xilinx.c card->u.xilinx.fifo_addr_map |= reg << i;
xilinx 3428 dev/pci/if_san_xilinx.c card->devname, card->u.xilinx.fifo_addr_map, i);
xilinx 3453 dev/pci/if_san_xilinx.c reg << sc->fifo_base_addr, card->u.xilinx.fifo_addr_map);
xilinx 3455 dev/pci/if_san_xilinx.c card->u.xilinx.fifo_addr_map &= ~(reg << sc->fifo_base_addr);
xilinx 3459 dev/pci/if_san_xilinx.c card->devname, card->u.xilinx.fifo_addr_map);
xilinx 3539 dev/pci/if_san_xilinx.c timeout_add(&card->u.xilinx.led_timer, hz);