wr                203 dev/ic/bt463.c bt463_register(v, sched_update, wr, rd)
wr                206 dev/ic/bt463.c 	void (*wr)(void *, u_int, u_int8_t);
wr                220 dev/ic/bt463.c 	data->ramdac_wr = wr;
wr                231 dev/ic/bt463.c bt463_cninit(v, sched_update, wr, rd)
wr                234 dev/ic/bt463.c 	void (*wr)(void *, u_int, u_int8_t);
wr                240 dev/ic/bt463.c 	data->ramdac_wr = wr;
wr                147 dev/ic/bt485.c bt485_register(v, sched_update, wr, rd)
wr                150 dev/ic/bt485.c 	void (*wr)(void *, u_int, u_int8_t);
wr                164 dev/ic/bt485.c 	data->ramdac_wr = wr;
wr                175 dev/ic/bt485.c bt485_cninit(v, sched_update, wr, rd)
wr                178 dev/ic/bt485.c 	void (*wr)(void *, u_int, u_int8_t);
wr                184 dev/ic/bt485.c 	data->ramdac_wr = wr;
wr                153 dev/ic/ibm561.c ibm561_register(v, sched_update, wr, rd)
wr                156 dev/ic/ibm561.c 	void (*wr)(void *, u_int, u_int8_t);
wr                168 dev/ic/ibm561.c 	data->ramdac_wr = wr;
wr                180 dev/ic/ibm561.c ibm561_cninit(v, sched_update, wr, rd, dotclock)
wr                183 dev/ic/ibm561.c 	void (*wr)(void *, u_int, u_int8_t);
wr                190 dev/ic/ibm561.c 	data->ramdac_wr = wr;
wr                702 dev/pci/noct.c 	u_int32_t reg, rd, wr;
wr                707 dev/pci/noct.c 	wr = (reg & RNGQPTR_WRITE_M) >> RNGQPTR_WRITE_S;
wr                709 dev/pci/noct.c 	while (rd != wr && cons < 32) {