tgt 733 dev/ic/ciss.c cmd->tgt = htole32(CISS_CMD_MODE_PERIPH);
tgt 765 dev/ic/ciss.c cmd->tgt = CISS_CMD_MODE_PERIPH;
tgt 782 dev/ic/ciss.c lmap->map[0].tgt, lmap->map[0].tgt2));
tgt 805 dev/ic/ciss.c cmd->tgt = CISS_CMD_MODE_PERIPH;
tgt 917 dev/ic/ciss.c cmd->tgt = CISS_CMD_MODE_LD | target;
tgt 1244 dev/ic/ciss.c cmd->tgt = htole32(CISS_CMD_MODE_PERIPH);
tgt 1272 dev/ic/ciss.c cmd->tgt = htole32(CISS_CMD_MODE_PERIPH);
tgt 1300 dev/ic/ciss.c cmd->tgt = htole32(CISS_CMD_MODE_PERIPH);
tgt 1371 dev/ic/ciss.c cmd->tgt = htole32(CISS_CMD_MODE_PERIPH);
tgt 127 dev/ic/cissreg.h u_int32_t tgt;
tgt 407 dev/ic/cissreg.h u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */
tgt 1043 dev/ic/isp.c int tgt;
tgt 1064 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 1068 dev/ic/isp.c if (sdp->isp_devparam[tgt].dev_enable == 0) {
tgt 1072 dev/ic/isp.c sdf = sdp->isp_devparam[tgt].goal_flags;
tgt 1092 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags = sdf = DPARM_DEFAULT;
tgt 1095 dev/ic/isp.c mbs.param[1] = (channel << 15) | (tgt << 8);
tgt 1101 dev/ic/isp.c (sdp->isp_devparam[tgt].goal_offset << 8) |
tgt 1102 dev/ic/isp.c (sdp->isp_devparam[tgt].goal_period);
tgt 1106 dev/ic/isp.c channel, tgt, mbs.param[2], mbs.param[3] >> 8,
tgt 1112 dev/ic/isp.c mbs.param[1] = (tgt << 8) | (channel << 15);
tgt 1132 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = sdf & ~DPARM_TQING;
tgt 1135 dev/ic/isp.c mbs.param[1] = (channel << 15) | (tgt << 8) | lun;
tgt 1137 dev/ic/isp.c mbs.param[3] = sdp->isp_devparam[tgt].exc_throttle;
tgt 1144 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 1145 dev/ic/isp.c if (sdp->isp_devparam[tgt].dev_refresh) {
tgt 3301 dev/ic/isp.c int bus, tgt;
tgt 3337 dev/ic/isp.c tgt = (*((int *) arg)) & 0xffff;
tgt 3340 dev/ic/isp.c mbs.param[1] = (tgt << 8) | (bus << 15);
tgt 3347 dev/ic/isp.c "Target %d on Bus %d Reset Succeeded", tgt, bus);
tgt 3353 dev/ic/isp.c tgt = XS_TGT(xs);
tgt 3364 dev/ic/isp.c mbs.param[1] = tgt << 8;
tgt 3369 dev/ic/isp.c mbs.param[1] = tgt << 8 | XS_LUN(xs);
tgt 5469 dev/ic/isp.c int tgt;
tgt 5483 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 5487 dev/ic/isp.c if (sdp->isp_devparam[tgt].dev_enable == 0) {
tgt 5488 dev/ic/isp.c sdp->isp_devparam[tgt].dev_update = 0;
tgt 5489 dev/ic/isp.c sdp->isp_devparam[tgt].dev_refresh = 0;
tgt 5491 dev/ic/isp.c "skipping target %d bus %d update", tgt, bus);
tgt 5504 dev/ic/isp.c if (sdp->isp_devparam[tgt].dev_refresh) {
tgt 5506 dev/ic/isp.c sdp->isp_devparam[tgt].dev_refresh = 0;
tgt 5508 dev/ic/isp.c } else if (sdp->isp_devparam[tgt].dev_update) {
tgt 5514 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags |= DPARM_RENEG;
tgt 5515 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags &= ~DPARM_QFRZ;
tgt 5517 dev/ic/isp.c mbs.param[2] = sdp->isp_devparam[tgt].goal_flags;
tgt 5531 dev/ic/isp.c (sdp->isp_devparam[tgt].goal_offset << 8) |
tgt 5532 dev/ic/isp.c (sdp->isp_devparam[tgt].goal_period);
tgt 5545 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags &= ~DPARM_TQING;
tgt 5546 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags |=
tgt 5547 dev/ic/isp.c (sdp->isp_devparam[tgt].goal_flags & DPARM_TQING);
tgt 5550 dev/ic/isp.c bus, tgt, mbs.param[2], mbs.param[3] >> 8,
tgt 5552 dev/ic/isp.c sdp->isp_devparam[tgt].dev_update = 0;
tgt 5553 dev/ic/isp.c sdp->isp_devparam[tgt].dev_refresh = 1;
tgt 5558 dev/ic/isp.c mbs.param[1] = (bus << 15) | (tgt << 8);
tgt 5567 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = flags;
tgt 5568 dev/ic/isp.c sdp->isp_devparam[tgt].actv_period = period;
tgt 5569 dev/ic/isp.c sdp->isp_devparam[tgt].actv_offset = offset;
tgt 5570 dev/ic/isp.c get = (bus << 16) | tgt;
tgt 5574 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 5575 dev/ic/isp.c if (sdp->isp_devparam[tgt].dev_update ||
tgt 5576 dev/ic/isp.c sdp->isp_devparam[tgt].dev_refresh) {
tgt 5593 dev/ic/isp.c int tgt;
tgt 5712 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 5713 dev/ic/isp.c sdp->isp_devparam[tgt].exc_throttle = ISP_EXEC_THROTTLE;
tgt 5714 dev/ic/isp.c sdp->isp_devparam[tgt].dev_enable = 1;
tgt 5762 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 5764 dev/ic/isp.c sdp->isp_devparam[tgt].actv_offset = 0;
tgt 5765 dev/ic/isp.c sdp->isp_devparam[tgt].actv_period = 0;
tgt 5766 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = 0;
tgt 5768 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags =
tgt 5769 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags = DPARM_DEFAULT;
tgt 5796 dev/ic/isp.c sdp->isp_devparam[tgt].goal_offset =
tgt 5797 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset = off;
tgt 5798 dev/ic/isp.c sdp->isp_devparam[tgt].goal_period =
tgt 5799 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period = per;
tgt 5802 dev/ic/isp.c channel, tgt, sdp->isp_devparam[tgt].nvrm_flags,
tgt 5803 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset,
tgt 5804 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period);
tgt 6001 dev/ic/isp.c int tgt;
tgt 6065 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 6066 dev/ic/isp.c sdp->isp_devparam[tgt].dev_enable =
tgt 6067 dev/ic/isp.c ISP_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt);
tgt 6068 dev/ic/isp.c sdp->isp_devparam[tgt].exc_throttle =
tgt 6069 dev/ic/isp.c ISP_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt);
tgt 6070 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset =
tgt 6071 dev/ic/isp.c ISP_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt);
tgt 6072 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period =
tgt 6073 dev/ic/isp.c ISP_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt);
tgt 6084 dev/ic/isp.c if (sdp->isp_devparam[tgt].nvrm_period < 0x19) {
tgt 6085 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period = 0x19;
tgt 6087 dev/ic/isp.c if (sdp->isp_devparam[tgt].nvrm_offset > 0xc) {
tgt 6088 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset = 0x0c;
tgt 6091 dev/ic/isp.c if (sdp->isp_devparam[tgt].nvrm_offset > 0x8) {
tgt 6092 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset = 0x8;
tgt 6095 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags = 0;
tgt 6096 dev/ic/isp.c if (ISP_NVRAM_TGT_RENEG(nvram_data, tgt))
tgt 6097 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG;
tgt 6098 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ;
tgt 6099 dev/ic/isp.c if (ISP_NVRAM_TGT_TQING(nvram_data, tgt))
tgt 6100 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING;
tgt 6101 dev/ic/isp.c if (ISP_NVRAM_TGT_SYNC(nvram_data, tgt))
tgt 6102 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC;
tgt 6103 dev/ic/isp.c if (ISP_NVRAM_TGT_WIDE(nvram_data, tgt))
tgt 6104 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE;
tgt 6105 dev/ic/isp.c if (ISP_NVRAM_TGT_PARITY(nvram_data, tgt))
tgt 6106 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY;
tgt 6107 dev/ic/isp.c if (ISP_NVRAM_TGT_DISC(nvram_data, tgt))
tgt 6108 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC;
tgt 6109 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = 0; /* we don't know */
tgt 6111 dev/ic/isp.c 0, tgt, sdp->isp_devparam[tgt].nvrm_flags,
tgt 6112 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset,
tgt 6113 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period);
tgt 6114 dev/ic/isp.c sdp->isp_devparam[tgt].goal_offset =
tgt 6115 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset;
tgt 6116 dev/ic/isp.c sdp->isp_devparam[tgt].goal_period =
tgt 6117 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period;
tgt 6118 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags =
tgt 6119 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags;
tgt 6127 dev/ic/isp.c int tgt;
tgt 6178 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 6179 dev/ic/isp.c sdp->isp_devparam[tgt].dev_enable =
tgt 6180 dev/ic/isp.c ISP1080_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt, bus);
tgt 6181 dev/ic/isp.c sdp->isp_devparam[tgt].exc_throttle =
tgt 6182 dev/ic/isp.c ISP1080_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt, bus);
tgt 6183 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset =
tgt 6184 dev/ic/isp.c ISP1080_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt, bus);
tgt 6185 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period =
tgt 6186 dev/ic/isp.c ISP1080_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt, bus);
tgt 6187 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags = 0;
tgt 6188 dev/ic/isp.c if (ISP1080_NVRAM_TGT_RENEG(nvram_data, tgt, bus))
tgt 6189 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG;
tgt 6190 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ;
tgt 6191 dev/ic/isp.c if (ISP1080_NVRAM_TGT_TQING(nvram_data, tgt, bus))
tgt 6192 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING;
tgt 6193 dev/ic/isp.c if (ISP1080_NVRAM_TGT_SYNC(nvram_data, tgt, bus))
tgt 6194 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC;
tgt 6195 dev/ic/isp.c if (ISP1080_NVRAM_TGT_WIDE(nvram_data, tgt, bus))
tgt 6196 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE;
tgt 6197 dev/ic/isp.c if (ISP1080_NVRAM_TGT_PARITY(nvram_data, tgt, bus))
tgt 6198 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY;
tgt 6199 dev/ic/isp.c if (ISP1080_NVRAM_TGT_DISC(nvram_data, tgt, bus))
tgt 6200 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC;
tgt 6201 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = 0;
tgt 6203 dev/ic/isp.c bus, tgt, sdp->isp_devparam[tgt].nvrm_flags,
tgt 6204 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset,
tgt 6205 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period);
tgt 6206 dev/ic/isp.c sdp->isp_devparam[tgt].goal_offset =
tgt 6207 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset;
tgt 6208 dev/ic/isp.c sdp->isp_devparam[tgt].goal_period =
tgt 6209 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period;
tgt 6210 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags =
tgt 6211 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags;
tgt 6219 dev/ic/isp.c int tgt;
tgt 6269 dev/ic/isp.c for (tgt = 0; tgt < MAX_TARGETS; tgt++) {
tgt 6270 dev/ic/isp.c sdp->isp_devparam[tgt].dev_enable =
tgt 6271 dev/ic/isp.c ISP12160_NVRAM_TGT_DEVICE_ENABLE(nvram_data, tgt, bus);
tgt 6272 dev/ic/isp.c sdp->isp_devparam[tgt].exc_throttle =
tgt 6273 dev/ic/isp.c ISP12160_NVRAM_TGT_EXEC_THROTTLE(nvram_data, tgt, bus);
tgt 6274 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset =
tgt 6275 dev/ic/isp.c ISP12160_NVRAM_TGT_SYNC_OFFSET(nvram_data, tgt, bus);
tgt 6276 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period =
tgt 6277 dev/ic/isp.c ISP12160_NVRAM_TGT_SYNC_PERIOD(nvram_data, tgt, bus);
tgt 6278 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags = 0;
tgt 6279 dev/ic/isp.c if (ISP12160_NVRAM_TGT_RENEG(nvram_data, tgt, bus))
tgt 6280 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_RENEG;
tgt 6281 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_ARQ;
tgt 6282 dev/ic/isp.c if (ISP12160_NVRAM_TGT_TQING(nvram_data, tgt, bus))
tgt 6283 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_TQING;
tgt 6284 dev/ic/isp.c if (ISP12160_NVRAM_TGT_SYNC(nvram_data, tgt, bus))
tgt 6285 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_SYNC;
tgt 6286 dev/ic/isp.c if (ISP12160_NVRAM_TGT_WIDE(nvram_data, tgt, bus))
tgt 6287 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_WIDE;
tgt 6288 dev/ic/isp.c if (ISP12160_NVRAM_TGT_PARITY(nvram_data, tgt, bus))
tgt 6289 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_PARITY;
tgt 6290 dev/ic/isp.c if (ISP12160_NVRAM_TGT_DISC(nvram_data, tgt, bus))
tgt 6291 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags |= DPARM_DISC;
tgt 6292 dev/ic/isp.c sdp->isp_devparam[tgt].actv_flags = 0;
tgt 6294 dev/ic/isp.c bus, tgt, sdp->isp_devparam[tgt].nvrm_flags,
tgt 6295 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset,
tgt 6296 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period);
tgt 6297 dev/ic/isp.c sdp->isp_devparam[tgt].goal_offset =
tgt 6298 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_offset;
tgt 6299 dev/ic/isp.c sdp->isp_devparam[tgt].goal_period =
tgt 6300 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_period;
tgt 6301 dev/ic/isp.c sdp->isp_devparam[tgt].goal_flags =
tgt 6302 dev/ic/isp.c sdp->isp_devparam[tgt].nvrm_flags;
tgt 202 dev/ic/isp_openbsd.c int tgt, chan;
tgt 218 dev/ic/isp_openbsd.c tgt = XS_TGT(xs);
tgt 222 dev/ic/isp_openbsd.c (isp->isp_osinfo.discovered[chan] & (1 << tgt)) != 0) {
tgt 244 dev/ic/isp_openbsd.c sdp->isp_devparam[tgt].goal_flags = f;
tgt 245 dev/ic/isp_openbsd.c sdp->isp_devparam[tgt].dev_update = 1;
tgt 257 dev/ic/isp_openbsd.c isp->isp_osinfo.discovered[chan] |= (1 << tgt);
tgt 685 dev/ic/isp_openbsd.c int bus, tgt;
tgt 694 dev/ic/isp_openbsd.c tgt = *((int *) arg);
tgt 695 dev/ic/isp_openbsd.c bus = (tgt >> 16) & 0xffff;
tgt 696 dev/ic/isp_openbsd.c tgt &= 0xffff;
tgt 698 dev/ic/isp_openbsd.c flags = sdp->isp_devparam[tgt].actv_flags;
tgt 699 dev/ic/isp_openbsd.c period = sdp->isp_devparam[tgt].actv_period;
tgt 702 dev/ic/isp_openbsd.c (sdp->isp_devparam[tgt].actv_offset) != 0) {
tgt 750 dev/ic/isp_openbsd.c bus, tgt, mhz, sdp->isp_devparam[tgt].actv_offset,
tgt 754 dev/ic/isp_openbsd.c "Bus %d Target %d Async Mode%s", bus, tgt, wt);
tgt 790 dev/ic/isp_openbsd.c int tgt = *((int *) arg);
tgt 791 dev/ic/isp_openbsd.c struct lportdb *lp = &fcp->portdb[tgt];
tgt 793 dev/ic/isp_openbsd.c isp_prt(isp, ISP_LOGINFO, fmt, tgt, lp->loopid, lp->portid,
tgt 282 dev/ic/isp_target.c isp_lun_cmd(struct ispsoftc *isp, int cmd, int bus, int tgt, int lun,
tgt 316 dev/ic/isp_target.c el.le_tgt = tgt;
tgt 727 dev/ic/ispreg.h #define _IxT(tgt, tidx) \
tgt 728 dev/ic/ispreg.h (ISP_NVRAM_TARGOFF + (ISP_NVARM_TARGSIZE * (tgt)) + (tidx))
tgt 822 dev/ic/ispreg.h #define _IxT8(tgt, tidx, b) \
tgt 823 dev/ic/ispreg.h (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
tgt 889 dev/ic/ispreg.h #define _IxT16(tgt, tidx, b) \
tgt 890 dev/ic/ispreg.h (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
tgt 294 dev/sdmmc/sdmmc_scsi.c struct sdmmc_scsi_target *tgt = &scbus->sc_tgt[link->target];
tgt 302 dev/sdmmc/sdmmc_scsi.c if (link->target >= scbus->sc_ntargets || tgt->card == NULL ||
tgt 352 dev/sdmmc/sdmmc_scsi.c _lto4b(tgt->card->csd.capacity - 1, rcd.addr);
tgt 353 dev/sdmmc/sdmmc_scsi.c _lto4b(tgt->card->csd.sector_size, rcd.length);
tgt 373 dev/sdmmc/sdmmc_scsi.c if (blockno >= tgt->card->csd.capacity ||
tgt 374 dev/sdmmc/sdmmc_scsi.c blockno + blockcnt > tgt->card->csd.capacity) {
tgt 376 dev/sdmmc/sdmmc_scsi.c blockno, blockcnt, tgt->card->csd.capacity));
tgt 436 dev/sdmmc/sdmmc_scsi.c struct sdmmc_scsi_target *tgt = &scbus->sc_tgt[link->target];
tgt 447 dev/sdmmc/sdmmc_scsi.c error = sdmmc_mem_read_block(tgt->card, ccb->ccb_blockno,
tgt 450 dev/sdmmc/sdmmc_scsi.c error = sdmmc_mem_write_block(tgt->card, ccb->ccb_blockno,