rng              1362 dev/pci/ubsec.c 		struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
rng              1366 dev/pci/ubsec.c 		bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0,
rng              1367 dev/pci/ubsec.c 		    rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
rng              1368 dev/pci/ubsec.c 		p = (u_int32_t *)rng->rng_buf.dma_vaddr;
rng              1371 dev/pci/ubsec.c 		rng->rng_used = 0;
rng              1457 dev/pci/ubsec.c 	struct ubsec_q2_rng *rng = &sc->sc_rng;
rng              1463 dev/pci/ubsec.c 	if (rng->rng_used) {
rng              1471 dev/pci/ubsec.c 	mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
rng              1472 dev/pci/ubsec.c 	ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
rng              1476 dev/pci/ubsec.c 	mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
rng              1480 dev/pci/ubsec.c 	mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
rng              1487 dev/pci/ubsec.c 	rng->rng_q.q_type = UBS_CTXOP_RNGSHA1;
rng              1489 dev/pci/ubsec.c 	bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0,
rng              1490 dev/pci/ubsec.c 	    rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD);
rng              1492 dev/pci/ubsec.c 	SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
rng              1493 dev/pci/ubsec.c 	rng->rng_used = 1;