phy_tmp          1582 dev/pci/if_em.c 		uint16_t phy_tmp = 0;
phy_tmp          1585 dev/pci/if_em.c 		em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
phy_tmp          1586 dev/pci/if_em.c 		phy_tmp &= ~IGP02E1000_PM_SPD;
phy_tmp          1587 dev/pci/if_em.c 		em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp);
phy_tmp          1703 dev/pci/if_em.c 	uint16_t phy_tmp;
phy_tmp          1712 dev/pci/if_em.c 		em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
phy_tmp          1713 dev/pci/if_em.c 		if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
phy_tmp          1715 dev/pci/if_em.c 		em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
phy_tmp          1716 dev/pci/if_em.c 		if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
phy_tmp          1718 dev/pci/if_em.c 					&phy_tmp);
phy_tmp          1719 dev/pci/if_em.c 			if (phy_tmp & CR_1000T_MS_ENABLE) {
phy_tmp          1720 dev/pci/if_em.c 				phy_tmp &= ~CR_1000T_MS_ENABLE;
phy_tmp          1722 dev/pci/if_em.c 						    PHY_1000T_CTRL, phy_tmp);
phy_tmp          1727 dev/pci/if_em.c 						       &phy_tmp)) {
phy_tmp          1728 dev/pci/if_em.c 					phy_tmp |= (MII_CR_AUTO_NEG_EN |  
phy_tmp          1731 dev/pci/if_em.c 							 PHY_CTRL, phy_tmp);
phy_tmp          1738 dev/pci/if_em.c 		em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
phy_tmp          1739 dev/pci/if_em.c 		phy_tmp |= CR_1000T_MS_ENABLE;
phy_tmp          1740 dev/pci/if_em.c 		em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
phy_tmp          1743 dev/pci/if_em.c 		    !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) {
phy_tmp          1744 dev/pci/if_em.c 			phy_tmp |= (MII_CR_AUTO_NEG_EN |
phy_tmp          1746 dev/pci/if_em.c 			em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp);