encl              610 dev/pci/hifn7751.c 	u_int32_t dmacfg, ramcfg, encl, addr, i;
encl              637 dev/pci/hifn7751.c 	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
encl              643 dev/pci/hifn7751.c 	if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
encl              650 dev/pci/hifn7751.c 	if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
encl              673 dev/pci/hifn7751.c 	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
encl              676 dev/pci/hifn7751.c 	if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
encl              686 dev/pci/hifn7751.c 	switch (encl) {