d_csr             941 dev/pci/safe.c 	re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI;
d_csr             943 dev/pci/safe.c 		re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL;
d_csr            1489 dev/pci/safe.c 			if (re->re_desc.d_csr != 0)
d_csr            1516 dev/pci/safe.c 	re->re_desc.d_csr = 0;
d_csr            1646 dev/pci/safe.c 	if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) {
d_csr            1648 dev/pci/safe.c 		    sc->sc_dev.dv_xname, re->re_desc.d_csr,
d_csr            1765 dev/pci/safe.c 			if (re->re_desc.d_csr != 0) {
d_csr            1766 dev/pci/safe.c 				if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr))
d_csr            2076 dev/pci/safe.c 	    re, ix, re->re_desc.d_csr, re->re_desc.d_src, re->re_desc.d_dst,
d_csr             293 dev/pci/safereg.h 	volatile u_int32_t	d_csr;		/* per-packet control/status */