cz 204 dev/pci/cz.c #define CZ_PLX_READ(cz, reg) \
cz 205 dev/pci/cz.c bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg))
cz 206 dev/pci/cz.c #define CZ_PLX_WRITE(cz, reg, val) \
cz 207 dev/pci/cz.c bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \
cz 214 dev/pci/cz.c #define CZ_FPGA_READ(cz, reg) \
cz 215 dev/pci/cz.c bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg))
cz 216 dev/pci/cz.c #define CZ_FPGA_WRITE(cz, reg, val) \
cz 217 dev/pci/cz.c bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val))
cz 222 dev/pci/cz.c #define CZ_FWCTL_READ(cz, off) \
cz 223 dev/pci/cz.c bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \
cz 224 dev/pci/cz.c (cz)->cz_fwctl + (off))
cz 226 dev/pci/cz.c #define CZ_FWCTL_WRITE(cz, off, val) \
cz 227 dev/pci/cz.c bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \
cz 228 dev/pci/cz.c (cz)->cz_fwctl + (off), (val))
cz 250 dev/pci/cz.c #define CZ_WIN_RAM(cz) \
cz 252 dev/pci/cz.c CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \
cz 256 dev/pci/cz.c #define CZ_WIN_FPGA(cz) \
cz 258 dev/pci/cz.c CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \
cz 294 dev/pci/cz.c struct cz_softc *cz = (void *) self;
cz 303 dev/pci/cz.c cz->cz_plx.plx_pc = pa->pa_pc;
cz 304 dev/pci/cz.c cz->cz_plx.plx_tag = pa->pa_tag;
cz 308 dev/pci/cz.c &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) {
cz 314 dev/pci/cz.c &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) {
cz 319 dev/pci/cz.c cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0);
cz 320 dev/pci/cz.c cz->cz_nopenchan = 0;
cz 325 dev/pci/cz.c CZ_WIN_FPGA(cz);
cz 326 dev/pci/cz.c CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0);
cz 331 dev/pci/cz.c if (cz_load_firmware(cz) != 0)
cz 346 dev/pci/cz.c cz->cz_ih = NULL;
cz 350 dev/pci/cz.c cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY,
cz 351 dev/pci/cz.c cz_intr, cz, cz->cz_dev.dv_xname);
cz 353 dev/pci/cz.c if (cz->cz_ih == NULL) {
cz 363 dev/pci/cz.c if (cz->cz_ih == NULL) {
cz 364 dev/pci/cz.c timeout_set(&cz->cz_timeout, cz_poll, cz);
cz 368 dev/pci/cz.c cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks,
cz 384 dev/pci/cz.c CZ_WIN_RAM(cz);
cz 386 dev/pci/cz.c if (cz->cz_nchannels == 0) {
cz 391 dev/pci/cz.c cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels,
cz 393 dev/pci/cz.c cztty_attached_ttys += cz->cz_nchannels;
cz 394 dev/pci/cz.c memset(cz->cz_ports, 0,
cz 395 dev/pci/cz.c sizeof(struct cztty_softc) * cz->cz_nchannels);
cz 397 dev/pci/cz.c for (i = 0; i < cz->cz_nchannels; i++) {
cz 398 dev/pci/cz.c sc = &cz->cz_ports[i];
cz 401 dev/pci/cz.c sc->sc_chan_st = cz->cz_win_st;
cz 402 dev/pci/cz.c sc->sc_parent = cz;
cz 404 dev/pci/cz.c if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh,
cz 405 dev/pci/cz.c cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0),
cz 408 dev/pci/cz.c cz->cz_dev.dv_xname, i);
cz 412 dev/pci/cz.c if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh,
cz 413 dev/pci/cz.c cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0),
cz 416 dev/pci/cz.c cz->cz_dev.dv_xname, i);
cz 425 dev/pci/cz.c (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i);
cz 451 dev/pci/cz.c cz_reset_board(struct cz_softc *cz)
cz 455 dev/pci/cz.c reg = CZ_PLX_READ(cz, PLX_CONTROL);
cz 456 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR);
cz 459 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
cz 463 dev/pci/cz.c reg = CZ_PLX_READ(cz, PLX_CONTROL);
cz 464 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG);
cz 466 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_CONTROL, reg);
cz 476 dev/pci/cz.c cz_load_firmware(struct cz_softc *cz)
cz 491 dev/pci/cz.c cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff));
cz 500 dev/pci/cz.c if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 &&
cz 506 dev/pci/cz.c cz->cz_dev.dv_xname);
cz 518 dev/pci/cz.c if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1
cz 520 dev/pci/cz.c && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0)
cz 524 dev/pci/cz.c printf("%s: Loading FPGA...", cz->cz_dev.dv_xname);
cz 526 dev/pci/cz.c CZ_WIN_FPGA(cz);
cz 535 dev/pci/cz.c bus_space_write_1(cz->cz_win_st,
cz 536 dev/pci/cz.c cz->cz_win_sh, 0, *cp);
cz 548 dev/pci/cz.c CZ_WIN_RAM(cz);
cz 560 dev/pci/cz.c bus_space_write_4(cz->cz_win_st, cz->cz_win_sh,
cz 568 dev/pci/cz.c CZ_WIN_FPGA(cz);
cz 569 dev/pci/cz.c CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0);
cz 572 dev/pci/cz.c CZ_WIN_RAM(cz);
cz 575 dev/pci/cz.c printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname);
cz 578 dev/pci/cz.c fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh,
cz 589 dev/pci/cz.c "problem\n", cz->cz_dev.dv_xname);
cz 603 dev/pci/cz.c CZ_WIN_FPGA(cz);
cz 605 dev/pci/cz.c cz->cz_dev.dv_xname, ZFIRM_SIG, fid);
cz 607 dev/pci/cz.c cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID),
cz 608 dev/pci/cz.c CZ_FPGA_READ(cz, FPGA_VERSION));
cz 615 dev/pci/cz.c cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh,
cz 619 dev/pci/cz.c cz->cz_dev.dv_xname, cz->cz_fwctl);
cz 622 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD);
cz 623 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION);
cz 625 dev/pci/cz.c cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL);
cz 627 dev/pci/cz.c switch (cz->cz_mailbox0) {
cz 645 dev/pci/cz.c fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION);
cz 646 dev/pci/cz.c printf("%s: %s, ", cz->cz_dev.dv_xname, board);
cz 647 dev/pci/cz.c if (cz->cz_nchannels == 0)
cz 651 dev/pci/cz.c cz->cz_nchannels, cztty_attached_ttys,
cz 652 dev/pci/cz.c cztty_attached_ttys + (cz->cz_nchannels - 1));
cz 669 dev/pci/cz.c struct cz_softc *cz = arg;
cz 671 dev/pci/cz.c cz_intr(cz);
cz 672 dev/pci/cz.c timeout_add(&cz->cz_timeout, cz_timeout_ticks);
cz 690 dev/pci/cz.c struct cz_softc *cz = arg;
cz 694 dev/pci/cz.c while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) {
cz 696 dev/pci/cz.c channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL);
cz 697 dev/pci/cz.c param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM);
cz 700 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command);
cz 702 dev/pci/cz.c if (cz->cz_ports == NULL) {
cz 705 dev/pci/cz.c cz->cz_dev.dv_xname, channel);
cz 710 dev/pci/cz.c sc = &cz->cz_ports[channel];
cz 725 dev/pci/cz.c cz->cz_dev.dv_xname, channel);
cz 809 dev/pci/cz.c cz->cz_dev.dv_xname, sc->sc_channel, command);
cz 825 dev/pci/cz.c cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring)
cz 829 dev/pci/cz.c while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) {
cz 830 dev/pci/cz.c error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100));
cz 852 dev/pci/cz.c struct cz_softc *cz;
cz 856 dev/pci/cz.c cz = (struct cz_softc *)device_lookup(&cz_cd, i);
cz 857 dev/pci/cz.c if (cz == NULL)
cz 859 dev/pci/cz.c if (cz->cz_ports == NULL)
cz 861 dev/pci/cz.c j += cz->cz_nchannels;
cz 869 dev/pci/cz.c return (&cz->cz_ports[u - k]);
cz 911 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 930 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czdis");
cz 932 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 933 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL);
cz 935 dev/pci/cz.c if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) {
cz 937 dev/pci/cz.c printf("%s: Disabling polling\n", cz->cz_dev.dv_xname);
cz 939 dev/pci/cz.c timeout_del(&cz->cz_timeout);
cz 954 dev/pci/cz.c struct cz_softc *cz;
cz 964 dev/pci/cz.c cz = CZTTY_CZ(sc);
cz 983 dev/pci/cz.c if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) {
cz 986 dev/pci/cz.c cz->cz_dev.dv_xname);
cz 988 dev/pci/cz.c timeout_add(&cz->cz_timeout, cz_timeout_ticks);
cz 995 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czopen");
cz 1218 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1220 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czbreak");
cz 1222 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 1223 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL,
cz 1235 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1240 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czmod");
cz 1248 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 1249 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
cz 1260 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1269 dev/pci/cz.c cz_wait_pci_doorbell(cz, "cztiocm");
cz 1288 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 1289 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
cz 1300 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1304 dev/pci/cz.c cz_wait_pci_doorbell(cz, "cztty");
cz 1340 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1441 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czparam");
cz 1449 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 1450 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW);
cz 1452 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czparam");
cz 1454 dev/pci/cz.c CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel);
cz 1455 dev/pci/cz.c CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM);
cz 1457 dev/pci/cz.c cz_wait_pci_doorbell(cz, "czparam");
cz 1528 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1549 dev/pci/cz.c cz->cz_dev.dv_xname, sc->sc_channel,
cz 1579 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1599 dev/pci/cz.c "transmit buf\n", cz->cz_dev.dv_xname,
cz 1606 dev/pci/cz.c bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh,
cz 1625 dev/pci/cz.c struct cz_softc *cz = CZTTY_CZ(sc);
cz 1640 dev/pci/cz.c ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh,