cmdr             1066 dev/ic/atw.c   	uint32_t cmdr;
cmdr             1067 dev/ic/atw.c   	cmdr = ATW_READ(sc, ATW_CMDR);
cmdr             1068 dev/ic/atw.c   	cmdr &= ~ATW_CMDR_APM;
cmdr             1069 dev/ic/atw.c   	cmdr |= ATW_CMDR_RTE;
cmdr             1070 dev/ic/atw.c   	cmdr &= ~ATW_CMDR_DRT_MASK;
cmdr             1071 dev/ic/atw.c   	cmdr |= ATW_CMDR_DRT_SF;
cmdr             1073 dev/ic/atw.c   	ATW_WRITE(sc, ATW_CMDR, cmdr);
cmdr               74 dev/ic/dc503reg.h 	volatile u_int16_t	cmdr;
cmdr              726 dev/pci/hifn7751.c 	    offsetof(struct hifn_dma, cmdr[0]));
cmdr              920 dev/pci/hifn7751.c 		dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
cmdr              988 dev/pci/hifn7751.c 	dma->cmdr[cmdi].l = htole32(16 | masks);
cmdr             1052 dev/pci/hifn7751.c 	dma->cmdr[cmdi].l = htole32(8 | masks);
cmdr             1102 dev/pci/hifn7751.c 		dma->cmdr[i].p = htole32(sc->sc_dmamap->dm_segs[0].ds_addr +
cmdr             1108 dev/pci/hifn7751.c 	dma->cmdr[HIFN_D_CMD_RSIZE].p =
cmdr             1110 dev/pci/hifn7751.c 		offsetof(struct hifn_dma, cmdr[0]));
cmdr             1531 dev/pci/hifn7751.c 		dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
cmdr             1541 dev/pci/hifn7751.c 	dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
cmdr             1784 dev/pci/hifn7751.c 		if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
cmdr             2533 dev/pci/hifn7751.c 		dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
cmdr             2543 dev/pci/hifn7751.c 	dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
cmdr               83 dev/pci/hifn7751var.h 	struct hifn_desc	cmdr[HIFN_D_CMD_RSIZE+1];
cmdr              114 dev/pci/hifn7751var.h #define	HIFN_CMDR_SYNC(sc, i, f)	HIFN_RING_SYNC((sc), cmdr, (i), (f))