1 /* $OpenBSD: gscsioreg.h,v 1.2 2004/11/17 16:53:05 mickey Exp $ */
2 /*
3 * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 /*
19 * National Semiconductor Geode SC1100 Super I/O register definitions.
20 */
21
22 #define GSCSIO_IOSIZE 2 /* I/O space size */
23
24 /* Index-data register pair */
25 #define GSCSIO_IDX 0x0 /* index register */
26 #define GSCSIO_DAT 0x1 /* data register */
27
28 /* SIO control and configuration registers */
29 #define GSCSIO_LDN 0x07 /* logical device number */
30 #define GSCSIO_LDN_ACB1 0x05 /* ACCESS.bus 1 */
31 #define GSCSIO_LDN_ACB2 0x06 /* ACCESS.bus 2 */
32 #define GSCSIO_ID 0x20 /* SIO ID */
33 #define GSCSIO_ID_SC1100 0xf5 /* Geode SC1100 ID */
34 #define GSCSIO_CFG1 0x21 /* configuration 1 */
35 #define GSCSIO_CFG2 0x22 /* configuration 2 */
36 #define GSCSIO_REV 0x27 /* revision ID */
37
38 /* Logical device control and configuration registers */
39 #define GSCSIO_ACT 0x30 /* logical device activation control */
40 #define GSCSIO_ACT_EN 0x01 /* enabled */
41 #define GSCSIO_IO0_MSB 0x60 /* I/O space 0 base bits [15:8] */
42 #define GSCSIO_IO0_LSB 0x61 /* I/O space 0 base bits [7:0] */
43 #define GSCSIO_IO1_MSB 0x62 /* I/O space 1 base bits [15:8] */
44 #define GSCSIO_IO1_LSB 0x63 /* I/O space 1 base bits [7:0] */
45 #define GSCSIO_INUM 0x70 /* interrupt number */
46 #define GSCSIO_ITYPE 0x71 /* interrupt type */
47 #define GSCSIO_DMA0 0x74 /* DMA channel 0 */
48 #define GSCSIO_DMA1 0x75 /* DMA channel 1 */
49
50 #define GSCSIO_LDNUM 6 /* total number of logical devices */
51
52 /* ACB (ACCESS.bus) logical device registers */
53 #define GSCSIO_ACB_SDA 0x00 /* serial data */
54 #define GSCSIO_ACB_ST 0x01 /* status */
55 #define GSCSIO_ACB_ST_XMIT (1 << 0) /* transmit mode active */
56 #define GSCSIO_ACB_ST_MASTER (1 << 1) /* master mode active */
57 #define GSCSIO_ACB_ST_NMATCH (1 << 2) /* new match */
58 #define GSCSIO_ACB_ST_STASTR (1 << 3) /* stall after start */
59 #define GSCSIO_ACB_ST_NEGACK (1 << 4) /* negative ack */
60 #define GSCSIO_ACB_ST_BER (1 << 5) /* bus error */
61 #define GSCSIO_ACB_ST_SDAST (1 << 6) /* wait or hold data */
62 #define GSCSIO_ACB_ST_SLVSTP (1 << 7) /* slave stop */
63 #define GSCSIO_ACB_CST 0x02 /* control status */
64 #define GSCSIO_ACB_CST_BUSY (1 << 0) /* busy */
65 #define GSCSIO_ACB_CST_BB (1 << 1) /* bus busy */
66 #define GSCSIO_ACB_CST_MATCH (1 << 2) /* match address */
67 #define GSCSIO_ACB_CST_GCMTCH (1 << 3) /* global call match */
68 #define GSCSIO_ACB_CST_TSDA (1 << 4) /* test ABD line */
69 #define GSCSIO_ACB_CST_TGABC (1 << 5) /* toggle ABC line */
70 #define GSCSIO_ACB_CTL1 0x03 /* control 1 */
71 #define GSCSIO_ACB_CTL1_START (1 << 0) /* start condition */
72 #define GSCSIO_ACB_CTL1_STOP (1 << 1) /* stop condition */
73 #define GSCSIO_ACB_CTL1_INTEN (1 << 2) /* interrupt enabled */
74 #define GSCSIO_ACB_CTL1_ACK (1 << 4) /* acknowledge */
75 #define GSCSIO_ACB_CTL1_GCMEN (1 << 5) /* global call match enable */
76 #define GSCSIO_ACB_CTL1_NMINTE (1 << 6) /* new match intr enable */
77 #define GSCSIO_ACB_CTL1_STASTRE (1 << 7) /* stall after start enable */
78 #define GSCSIO_ACB_ADDR 0x04 /* own address */
79 #define GSCSIO_ACB_ADDR_MASK 0x7f /* address mask */
80 #define GSCSIO_ACB_ADDR_SAEN (1 << 7) /* slave address enable */
81 #define GSCSIO_ACB_CTL2 0x05 /* control 2 */
82 #define GSCSIO_ACB_CTL2_EN (1 << 0) /* ACB enabled */
83 #define GSCSIO_ACB_CTL2_FREQ_SHIFT 1 /* ACB frequency shift */
84 #define GSCSIO_ACB_CTL2_FREQ_MASK 0x7f /* ACB frequency mask */
85
86 #define GSCSIO_ACB_FREQ 0x3c /* standard I2C frequency 100kHz */