1 /* $OpenBSD: mc6845.h,v 1.5 2005/12/12 12:35:49 mickey Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1995 Hellmuth Michaelis and Joerg Wunsch.
5 * Copyright (c) 1992, 1993 Brian Dunford-Shore.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by
19 * Hellmuth Michaelis, Brian Dunford-Shore and Joerg Wunsch.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 */
36
37
38 #define MONO_BASE 0x3B4 /* crtc index register address mono */
39 #define CGA_BASE 0x3D4 /* crtc index register address color */
40
41 #define CRTC_ADDR 0x00 /* index register */
42
43 #define CRTC_HTOTAL 0x00 /* horizontal total */
44 #define CRTC_HDISPLE 0x01 /* horizontal display end */
45 #define CRTC_HBLANKS 0x02 /* horizontal blank start */
46 #define CRTC_HBLANKE 0x03 /* horizontal blank end */
47 #define CRTC_HSYNCS 0x04 /* horizontal sync start */
48 #define CRTC_HSYNCE 0x05 /* horizontal sync end */
49 #define CRTC_VTOTAL 0x06 /* vertical total */
50 #define CRTC_OVERFLL 0x07 /* overflow low */
51 #define CRTC_IROWADDR 0x08 /* initial row address */
52 #define CRTC_MAXROW 0x09 /* maximum row address */
53 #define CRTC_CURSTART 0x0A /* cursor start row address */
54 #define CRTC_CUREND 0x0B /* cursor end row address */
55 #define CRTC_STARTADRH 0x0C /* linear start address mid */
56 #define CRTC_STARTADRL 0x0D /* linear start address low */
57 #define CRTC_CURSORH 0x0E /* cursor address mid */
58 #define CRTC_CURSORL 0x0F /* cursor address low */
59 #define CRTC_VSYNCS 0x10 /* vertical sync start */
60 #define CRTC_VSYNCE 0x11 /* vertical sync end */
61 #define CRTC_VDE 0x12 /* vertical display end */
62 #define CRTC_OFFSET 0x13 /* row offset */
63 #define CRTC_ULOC 0x14 /* underline row address */
64 #define CRTC_VBSTART 0x15 /* vertical blank start */
65 #define CRTC_VBEND 0x16 /* vertical blank end */
66 #define CRTC_MODE 0x17 /* CRTC mode register */
67 #define CRTC_SPLITL 0x18 /* split screen start low */
68
69 /* start of ET4000 extensions */
70
71 #define CRTC_RASCAS 0x32 /* ras/cas configuration */
72 #define CRTC_EXTSTART 0x33 /* extended start address */
73 #define CRTC_COMPAT6845 0x34 /* 6845 compatibility control */
74 #define CRTC_OVFLHIGH 0x35 /* overflow high */
75 #define CRTC_SYSCONF1 0x36 /* video system configuration 1 */
76 #define CRTC_SYSCONF2 0x36 /* video system configuration 2 */
77
78 /* start of WD/Paradise extensions */
79
80 #define CRTC_PR10 0x29 /* r/w unlocking */
81 #define CRTC_PR11 0x2A /* ega switches */
82 #define CRTC_PR12 0x2B /* scratch pad */
83 #define CRTC_PR13 0x2C /* interlace h/2 start */
84 #define CRTC_PR14 0x2D /* interlace h/2 end */
85 #define CRTC_PR15 0x2E /* misc control #1 */
86 #define CRTC_PR16 0x2F /* misc control #2 */
87 #define CRTC_PR17 0x30 /* misc control #3 */
88 /* 0x31 .. 0x3f reserved */
89 /* Video 7 */
90
91 #define CRTC_V7ID 0x1f /* identification register */
92
93 /* Trident */
94
95 #define CRTC_MTEST 0x1e /* module test register */
96 #define CRTC_SOFTPROG 0x1f /* software programming */
97 #define CRTC_LATCHRDB 0x22 /* latch read back register */
98 #define CRTC_ATTRSRDB 0x24 /* attribute state read back register*/
99 #define CRTC_ATTRIRDB 0x26 /* attribute index read back register*/
100 #define CRTC_HOSTAR 0x27 /* high order start address register */
101