1 /* $OpenBSD: ibm525reg.h,v 1.1 2005/07/19 09:34:14 miod Exp $ */
2 /*
3 * Copyright (c) 2005, Miodrag Vallat.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * IBM RGB525 Ramdac registers
29 */
30
31 #define IBM525_REVISION 0x00
32 #define IBM525_ID 0x01
33
34 /* Miscellaneous clock control */
35 #define IBM525_MISC_CLOCK 0x02
36 #define MC_B24P_PLL 0x00
37 #define MC_B24P_SCLK 0x20
38 #define MC_DDOT_DIV_1 0x00 /* (VRAM size / 1) bpp */
39 #define MC_DDOT_DIV_2 0x02 /* (VRAM size / 2) bpp */
40 #define MC_DDOT_DIV_4 0x04 /* (VRAM size / 4) bpp */
41 #define MC_DDOT_DIV_8 0x06 /* (VRAM size / 8) bpp */
42 #define MC_DDOT_DIV_16 0x08 /* (VRAM size / 16) bpp */
43 #define MC_DDOT_DIV_MASK 0x0e
44 #define MC_PLL_ENABLE 0x01
45
46 /* Sync control */
47 #define IBM525_SYNC 0x03
48 #define S_CSYN_INVERT 0x40 /* Composite sync invert */
49 #define S_VSYN_INVERT 0x20 /* Vertical sync invert (positive) */
50 #define S_HSYN_INVERT 0x10 /* Horizontal sync invert (positive) */
51 #define S_VSYN_NORMAL 0x00
52 #define S_VSYN_HIGH 0x04
53 #define S_VSYN_LOW 0x08
54 #define S_VSYN_DISABLE 0x0c
55 #define S_VSYN_MASK 0x0c
56 #define S_HSYN_NORMAL 0x00
57 #define S_HSYN_HIGH 0x01
58 #define S_HSYN_LOW 0x02
59 #define S_HSYN_DISABLE 0x03
60 #define S_HSYN_MASK 0x03
61
62 /* Horizontal sync position */
63 #define IBM525_HSYNC_POS 0x04
64
65 /* Power management */
66 #define IBM525_POWER 0x05
67 #define P_SCLK_DISABLE 0x10
68 #define P_DDOT_DISABLE 0x08
69 #define P_SYNC_DISABLE 0x04
70 #define P_ICLK_DISABLE 0x02 /* Disable internal DAC clock */
71 #define P_DAC_PWR_DISABLE 0x01 /* Disable internal DAC power */
72
73 /* DAC operation */
74 #define IBM525_DAC_OP 0x06
75 #define DO_SOG 0x08 /* Sync on Green */
76 #define DO_FAST_SLEW 0x02 /* fast (>= 20 MHz) pixel clock */
77 #define DO_BLANK_BR 0x04 /* blank blue and red channels */
78 #define DO_PEDESTAL 0x01
79
80 /* Palette control */
81 #define IBM525_PALETTE 0x07
82
83 /* System clock control */
84 #define IBM525_SYSCLK 0x08
85 #define SC_ENABLE 0x01
86
87 /* Pixel format */
88 #define IBM525_PIXEL 0x0a
89 #define PIX_4BPP 0x02
90 #define PIX_8BPP 0x03
91 #define PIX_16BPP 0x04
92 #define PIX_24BPP 0x05
93 #define PIX_32BPP 0x06
94
95 /* 8bpp pixel format */
96 #define IBM525_PF8 0x0b
97 #define PF8_INDIRECT 0x00
98 #define PF8_DIRECT 0x01
99
100 /* 16bpp pixel format */
101 #define IBM525_PF16 0x0c
102 #define PF16_INDIRECT 0x00
103 #define PF16_DIRECT 0xc0
104 #define PF16_LINEAR 0x04
105 #define PF16_555 0x00 /* 5:5:5 15bpp */
106 #define PF16_565 0x02 /* 5:6:5 15bpp */
107
108 /* 24bpp pixel format */
109 #define IBM525_PF24 0x0d
110 #define PF24_INDIRECT 0x00
111 #define PF24_DIRECT 0x01
112
113 /* 32bpp pixel format */
114 #define IBM525_PF32 0x0e
115 #define PF32_INDIRECT 0x00
116 #define PF32_DIRECT 0x03
117 #define PF32_BYPASS 0x00
118 #define PF32_LOOKUP 0x04
119
120 /* Pixel PLL control #1 */
121 #define IBM525_PLL1 0x10
122 #define P1_CLK_REF 0x00
123 #define P1_CLK_EXT 0x10
124 #define P1_SRC_EXT_F 0x00 /* Use F registers for timing */
125 #define P1_SRC_EXT_MN 0x01 /* Use M:N registers for timing */
126 #define P1_SRC_DIRECT_F 0x02 /* Use F registers for timing */
127 #define P1_SRC_DIRECT_MN 0x03 /* Use M:N registers for timing */
128
129 /* Pixel PLL control #2 */
130 #define IBM525_PLL2 0x11
131
132 /* Fixed PLL reference */
133 #define IBM525_PLL_FIXED_REF 0x14
134
135 /* PLL reference divider */
136 #define IBM525_PLL_REF_DIV 0x15
137
138 /* PLL VCO divider */
139 #define IBM525_PLL_VCO_DIV 0x16
140
141 /* N0-N15 */
142 #define IBM525_F(n) (0x20 + (n))
143
144 /* Miscellaneous control #1 */
145 #define IBM525_MISC1 0x70
146 #define M1_VRAM_32 0x00
147 #define M1_VRAM_64 0x01
148 #define M1_VRAM_SIZE_MASK 0x01
149 #define M1_SENSE_DISABLE 0x10
150
151 /* Miscellaneous control #2 */
152 #define IBM525_MISC2 0x71
153 #define M2_PCLK_LOCAL 0x00
154 #define M2_PCLK_PLL 0x40
155 #define M2_PCLK_EXT 0x80
156 #define M2_PCLK_MASK 0xc0
157 #define M2_PALETTE_6 0x00 /* VGA compatible 6bit palette */
158 #define M2_PALETTE_8 0x04 /* 8bit palette */
159 #define M2_PALETTE_MASK 0x04
160 #define M2_MODE_VRAM 0x01
161 #define M2_MODE_VGA 0x00
162 #define M2_MODE_MASK 0x01
163
164 /* Miscellaneous control #3 */
165 #define IBM525_MISC3 0x72
166 #define M3_SWAP_BR 0x80 /* swap blue and red */
167 #define M3_SWAP_WORDS 0x10
168 #define M3_SWAP_NIBBLES 0x02
169
170 /* Miscellaneous control #4 */
171 #define IBM525_MISC4 0x73
172 #define M4_INVERT_DCLK 0x10
173 #define M4_FAST 0x20 /* Fast (>= 50 MHz) pixel clock */
174
175 /*
176 * Pixel clock encoding
177 */
178 #define MHZ_TO_PLL(m) \
179 (m) < 32 ? 0x00 | (4 * (m) - 65) : \
180 (m) < 64 ? 0x40 | (2 * (m) - 65) : \
181 (m) < 128 ? 0x80 | ((m) - 65) : \
182 0xc0 | ((m) / 2 - 65)