rcr0              135 arch/i386/i386/autoconf.c 	proc0.p_addr->u_pcb.pcb_cr0 = rcr0();
rcr0              338 arch/i386/i386/cpu.c 	lcr0(rcr0() | CR0_WP);
rcr0              290 arch/i386/i386/i686_mem.c 	lcr0((rcr0() & ~CR0_NW) | CR0_CD); /* disable caches (CD = 1, NW = 0) */
rcr0              357 arch/i386/i386/i686_mem.c 	lcr0(rcr0() & ~(CR0_CD | CR0_NW));  			/* enable caches CD = 0 and NW = 0 */
rcr0              490 arch/i386/i386/machdep.c 	pcb->pcb_cr0 = rcr0();
rcr0              515 arch/i386/i386/machdep.c 	pcb->pcb_cr0 = rcr0();
rcr0             1847 arch/i386/i386/machdep.c 	lcr0(rcr0() | CR0_WP);
rcr0              154 arch/i386/i386/procfs_machdep.c 		(rcr0() & CR0_WP) ? "yes" : "no",
rcr0              329 arch/i386/i386/via.c 	creg0 = rcr0();		/* Permit access to SIMD/FPU path */
rcr0              545 arch/i386/i386/via.c 	creg0 = rcr0();		/* Permit access to SIMD/FPU path */
rcr0               53 arch/i386/include/cpufunc.h static __inline u_int rcr0(void);
rcr0               98 arch/i386/isa/npx.c #define	stts()			lcr0(rcr0() | CR0_TS)
rcr0              321 arch/i386/isa/npx.c 	lcr0(rcr0() & ~(CR0_EM|CR0_TS));
rcr0              325 arch/i386/isa/npx.c 	lcr0(rcr0() | (CR0_EM|CR0_TS));
rcr0              352 arch/i386/isa/npx.c 	lcr0(rcr0() & ~(CR0_EM|CR0_TS));
rcr0              359 arch/i386/isa/npx.c 	lcr0(rcr0() | (CR0_TS));
rcr0              374 arch/i386/isa/npx.c 		lcr0(rcr0() & ~CR0_NE);
rcr0              588 arch/i386/isa/npx.c 		printf("recursive npx trap; cr0=%x\n", rcr0());
rcr0              668 arch/i386/isa/npx.c 		printf("recursive npx trap; cr0=%x\n", rcr0());
rcr0             3922 dev/ic/rtw.c   	RTW_WRITE(regs, RTW_RCR, rcr0);	/* restore RCR */