BL3                60 dev/ic/osiopreg.h #define OSIOP_SIEN	(0x00+BL3)	/* rw: SCSI interrupt enable */
BL3                65 dev/ic/osiopreg.h #define OSIOP_SOCL	(0x04+BL3)	/* rw: SCSI Output Control Latch */
BL3                70 dev/ic/osiopreg.h #define OSIOP_SBCL	(0x08+BL3)	/* rw: SCSI Bus Control Lines */
BL3                75 dev/ic/osiopreg.h #define OSIOP_SSTAT2	(0x0c+BL3)	/* ro: SCSI status reg 2 */
BL3                82 dev/ic/osiopreg.h #define OSIOP_CTEST3	(0x14+BL3)	/* ro: Chip test register 3 */
BL3                87 dev/ic/osiopreg.h #define OSIOP_CTEST7	(0x18+BL3)	/* rw: Chip test register 7 */
BL3                94 dev/ic/osiopreg.h #define OSIOP_LCRC	(0x20+BL3)	/* rw: LCRC value */
BL3               100 dev/ic/osiopreg.h #define OSIOP_DCMD	(0x24+BL3)	/* rw: DMA Command Register */
BL3               113 dev/ic/osiopreg.h #define OSIOP_DCNTL	(0x38+BL3)	/* rw: DMA Control reg */