BL2                59 dev/ic/osiopreg.h #define OSIOP_SDID	(0x00+BL2)	/* rw: SCSI destination ID */
BL2                64 dev/ic/osiopreg.h #define OSIOP_SODL	(0x04+BL2)	/* rw: SCSI Output Data Latch */
BL2                69 dev/ic/osiopreg.h #define OSIOP_SBDL	(0x08+BL2)	/* ro: SCSI Bus Data Lines */
BL2                74 dev/ic/osiopreg.h #define OSIOP_SSTAT1	(0x0c+BL2)	/* ro: SCSI status reg 1 */
BL2                81 dev/ic/osiopreg.h #define OSIOP_CTEST2	(0x14+BL2)	/* ro: Chip test register 2 */
BL2                86 dev/ic/osiopreg.h #define OSIOP_CTEST6	(0x18+BL2)	/* rw: Chip test register 6 */
BL2                93 dev/ic/osiopreg.h #define OSIOP_CTEST8	(0x20+BL2)	/* rw: Chip test register 8 */
BL2                99 dev/ic/osiopreg.h #define OSIOP_DBC2	(0x24+BL2)	/* rw: DMA Byte Counter reg 2 */
BL2               112 dev/ic/osiopreg.h #define OSIOP_DWT	(0x38+BL2)	/* rw: DMA Watchdog Timer */