BL1                58 dev/ic/osiopreg.h #define OSIOP_SCNTL1	(0x00+BL1)	/* rw: SCSI control reg 1 */
BL1                63 dev/ic/osiopreg.h #define OSIOP_SXFER	(0x04+BL1)	/* rw: SCSI Transfer reg */
BL1                68 dev/ic/osiopreg.h #define OSIOP_SIDL	(0x08+BL1)	/* ro: SCSI Input Data Latch */
BL1                73 dev/ic/osiopreg.h #define OSIOP_SSTAT0	(0x0c+BL1)	/* ro: SCSI status reg 0 */
BL1                80 dev/ic/osiopreg.h #define OSIOP_CTEST1	(0x14+BL1)	/* ro: Chip test register 1 */
BL1                85 dev/ic/osiopreg.h #define OSIOP_CTEST5	(0x18+BL1)	/* rw: Chip test register 5 */
BL1                92 dev/ic/osiopreg.h #define OSIOP_ISTAT	(0x20+BL1)	/* rw: Interrupt Status reg */
BL1                98 dev/ic/osiopreg.h #define OSIOP_DBC1	(0x24+BL1)	/* rw: DMA Byte Counter reg 1 */
BL1               111 dev/ic/osiopreg.h #define OSIOP_DIEN	(0x38+BL1)	/* rw: DMA Interrupt Enable */