lmc_t1_write      841 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x01, 0x1B);  /* CR0     - primary control          */
lmc_t1_write      842 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x02, 0x42);  /* JAT_CR  - jitter atten config      */
lmc_t1_write      843 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x14, 0x00);  /* LOOP    - loopback config          */
lmc_t1_write      844 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x15, 0x00);  /* DL3_TS  - xtrnl datalink timeslot  */
lmc_t1_write      845 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x18, 0xFF);  /* PIO     - programmable I/O         */
lmc_t1_write      846 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x19, 0x30);  /* POE     - programmable OE          */
lmc_t1_write      847 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x1A, 0x0F);  /* CMUX    - clock input mux          */
lmc_t1_write      848 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x20, 0x41);  /* LIU_CR  - RX LIU config            */
lmc_t1_write      849 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x22, 0x76);  /* RLIU_CR - RX LIU config            */
lmc_t1_write      850 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x40, 0x03);  /* RCR0    - RX config                */
lmc_t1_write      851 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x45, 0x00);  /* RALM    - RX alarm config          */
lmc_t1_write      852 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x46, 0x05);  /* LATCH   - RX alarm/err/cntr latch  */
lmc_t1_write      853 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x68, 0x40);  /* TLIU_CR - TX LIU config            */
lmc_t1_write      854 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x70, 0x0D);  /* TCR0    - TX framer config         */
lmc_t1_write      855 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x71, 0x05);  /* TCR1    - TX config                */
lmc_t1_write      856 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x72, 0x0B);  /* TFRM    - TX frame format          */
lmc_t1_write      857 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x73, 0x00);  /* TERROR  - TX error insert          */
lmc_t1_write      858 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x74, 0x00);  /* TMAN    - TX manual Sa/FEBE config */
lmc_t1_write      859 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x75, 0x00);  /* TALM    - TX alarm signal config   */
lmc_t1_write      860 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x76, 0x00);  /* TPATT   - TX test pattern config   */
lmc_t1_write      861 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x77, 0x00);  /* TLB     - TX inband loopback confg */
lmc_t1_write      862 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x90, 0x05);  /* CLAD_CR - clock rate adapter confg */
lmc_t1_write      863 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0x91, 0x05);  /* CSEL    - clad freq sel            */
lmc_t1_write      864 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0xA6, 0x00);  /* DL1_CTL - DL1 control              */
lmc_t1_write      865 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0xB1, 0x00);  /* DL2_CTL - DL2 control              */
lmc_t1_write      866 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0xD0, 0x47);  /* SBI_CR  - sys bus iface config     */
lmc_t1_write      867 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0xD1, 0x70);  /* RSB_CR  - RX sys bus config        */
lmc_t1_write      868 dev/pci/if_lmc_media.c         lmc_t1_write(sc, 0xD4, 0x30);  /* TSB_CR  - TX sys bus config        */
lmc_t1_write      871 dev/pci/if_lmc_media.c                 lmc_t1_write(sc, 0x0E0+i, 0x00); /*SBCn sysbus perchannel ctl */
lmc_t1_write      872 dev/pci/if_lmc_media.c                 lmc_t1_write(sc, 0x100+i, 0x00); /* TPCn - TX per-channel ctl */
lmc_t1_write      873 dev/pci/if_lmc_media.c                 lmc_t1_write(sc, 0x180+i, 0x00); /* RPCn - RX per-channel ctl */
lmc_t1_write      876 dev/pci/if_lmc_media.c 	{                lmc_t1_write(sc, 0x0E0+i, 0x0D);