csr_srom_mii       95 dev/pci/if_de.c #define EMIT	do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); tulip_delay_300ns(sc); } while (0)
csr_srom_mii       96 dev/pci/if_de.c #define MII_EMIT	do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); tulip_delay_300ns(sc); } while (0)
csr_srom_mii     1829 dev/pci/if_de.c             data |= TULIP_CSR_READ(sc, csr_srom_mii) & SROMDIN ? 1 : 0;
csr_srom_mii     1844 dev/pci/if_de.c     unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii     1862 dev/pci/if_de.c     unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii     1879 dev/pci/if_de.c     unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii     1885 dev/pci/if_de.c 	if (TULIP_CSR_READ(sc, csr_srom_mii) & MII_DIN)
csr_srom_mii     1897 dev/pci/if_de.c     unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii     1921 dev/pci/if_de.c     csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii      144 dev/pci/if_lmc.c 	LMC_CSR_WRITE(sc, csr_srom_mii, csr); \
csr_srom_mii      208 dev/pci/if_lmc.c 			data |= LMC_CSR_READ(sc, csr_srom_mii) & SROMDIN ? 1 : 0;
csr_srom_mii      219 dev/pci/if_lmc.c #define MII_EMIT    do { LMC_CSR_WRITE(sc, csr_srom_mii, csr); lmc_delay_300ns(sc); } while (0)
csr_srom_mii      225 dev/pci/if_lmc.c     unsigned csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii      246 dev/pci/if_lmc.c     csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii      263 dev/pci/if_lmc.c     u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii      269 dev/pci/if_lmc.c 	if (LMC_CSR_READ(sc, csr_srom_mii) & MII_DIN)
csr_srom_mii      281 dev/pci/if_lmc.c     u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr_srom_mii      301 dev/pci/if_lmc.c     csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);