che_write 292 dev/pci/if_che.c void che_write(struct cheg_softc *, bus_size_t, u_int32_t); che_write 501 dev/pci/if_che.c che_write(sc, CHE_REG_SF_DATA, v); che_write 502 dev/pci/if_che.c che_write(sc, CHE_REG_SF_OP, CHE_SF_CONT(cont) | che_write 514 dev/pci/if_che.c che_write(sc, CHE_REG_SF_OP, CHE_SF_CONT(cont) | che_write 653 dev/pci/if_che.c che_write(sc, CHE_REG_PL_RST, CHE_RST_F_CRSTWRM | che_write 703 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, addr); che_write 704 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(2)); che_write 718 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, addr); che_write 719 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, val); che_write 720 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(1)); che_write 729 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, CHE_MI1_PHYADDR(phy)); che_write 730 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, reg); che_write 731 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(0)); che_write 736 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(3)); che_write 749 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_ADDR, CHE_MI1_PHYADDR(phy)); che_write 750 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, reg); che_write 751 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(0)); che_write 756 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_DATA, val); che_write 757 dev/pci/if_che.c che_write(sc->sc_cheg, CHE_REG_MI1_OP, CHE_MI1_OP(1)); che_write 862 dev/pci/if_che.c che_write(sc, CHE_REG_MI1_CFG, mi1_reg); che_write 863 dev/pci/if_che.c che_write(sc, CHE_REG_I2C_CFG, i2c_reg); che_write 864 dev/pci/if_che.c che_write(sc, CHE_REG_T3DBG_GPIO_EN, gpio_reg); che_write 866 dev/pci/if_che.c che_write(sc, CHE_REG_XGM_PORT_CFG, port_reg); che_write 871 dev/pci/if_che.c che_write(sc, CHE_REG_XGM_PORT_CFG, port_reg); che_write 873 dev/pci/if_che.c che_write(sc, CHE_XGM_REG(CHE_REG_XGM_PORT_CFG, 1), port_reg);