bit_set           219 dev/pci/if_san_common.c 	bit_set((u_int8_t*)&card->critical, PERI_CRIT);
bit_set          2401 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED);
bit_set          2470 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_KILL);
bit_set          3659 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_RUNNING);
bit_set          3773 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_WAITING);
bit_set          3774 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CODE_BIT);
bit_set          3775 dev/pci/if_san_te1.c 	bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CHANNEL_BIT);
bit_set           554 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&card->critical, CARD_DOWN);
bit_set           795 dev/pci/if_san_xilinx.c 					bit_set((u_int8_t *)
bit_set           802 dev/pci/if_san_xilinx.c 					bit_set((u_int8_t *)
bit_set           807 dev/pci/if_san_xilinx.c 				bit_set((u_int8_t *)&
bit_set           973 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, FRONT_END_FRAME_FLAG_ENABLE_BIT);
bit_set           976 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, INTERFACE_TYPE_T1_E1_BIT);
bit_set           977 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, FRONT_END_FRAME_FLAG_ENABLE_BIT);
bit_set           994 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, FRONT_END_RESET_BIT);
bit_set          1004 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, CHIP_RESET_BIT);
bit_set          1056 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, XILINX_RED_LED);
bit_set          1084 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, CHIP_RESET_BIT);
bit_set          1109 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, DMA_ENGINE_ENABLE_BIT);
bit_set          1138 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, CHIP_RESET_BIT);
bit_set          1148 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, CHIP_RESET_BIT);
bit_set          1159 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, FRONT_END_INTR_ENABLE_BIT);
bit_set          1181 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, CHIP_RESET_BIT);
bit_set          1272 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&card->u.xilinx.time_slot_map, i);
bit_set          1379 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&reg, HDLC_RX_ADDR_RECOGN_DIS_BIT);
bit_set          1401 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, HDLC_TX_CHAN_ENABLE_BIT);
bit_set          1402 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, HDLC_RX_ADDR_RECOGN_DIS_BIT);
bit_set          1498 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, INIT_DMA_FIFO_CMD_BIT);
bit_set          1547 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, INIT_DMA_FIFO_CMD_BIT);
bit_set          1594 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, sc->logic_ch_num);
bit_set          1598 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&card->u.xilinx.active_ch_map, sc->logic_ch_num);
bit_set          1735 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, RxDMA_HI_DMA_GO_READY_BIT);
bit_set          1744 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&sc->rx_dma, 0);
bit_set          1770 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&sc->dma_status, TX_BUSY);
bit_set          1911 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, TxDMA_HI_DMA_FRAME_START_BIT);
bit_set          1912 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, TxDMA_HI_DMA_FRAME_END_BIT);
bit_set          1914 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, TxDMA_HI_DMA_GO_READY_BIT);
bit_set          1968 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&reg,
bit_set          2051 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&sc->idle_start, 0);
bit_set          2203 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&rx_el->pkt_error,
bit_set          2219 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&rx_el->pkt_error,
bit_set          2245 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)pkt_error, WP_FIFO_ERROR_BIT);
bit_set          2251 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)pkt_error, WP_FIFO_ERROR_BIT);
bit_set          2310 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&card->u.xilinx.logic_ch_map, i);
bit_set          2681 dev/pci/if_san_xilinx.c 				bit_set((u_int8_t *)&sc->pkt_error,
bit_set          2723 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&card->in_isr, 0);
bit_set          3061 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, DMA_ENGINE_ENABLE_BIT);
bit_set          3152 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, GLOBAL_INTR_ENABLE_BIT);
bit_set          3153 dev/pci/if_san_xilinx.c 	bit_set((u_int8_t *)&reg, ERROR_INTR_ENABLE_BIT);
bit_set          3414 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, i);
bit_set          3449 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&reg, i);
bit_set          3478 dev/pci/if_san_xilinx.c 		bit_set((u_int8_t *)&led, XILINX_RED_LED);
bit_set          3483 dev/pci/if_san_xilinx.c 			bit_set((u_int8_t *)&led, XILINX_RED_LED);