BA0READ4 324 dev/pci/cs4280.c BA0READ4(sc, CS4280_ACSDA);
BA0READ4 340 dev/pci/cs4280.c while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) {
BA0READ4 348 dev/pci/cs4280.c *data = BA0READ4(sc, CS4280_ACSDA);
BA0READ4 382 dev/pci/cs4280.c while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) {
BA0READ4 701 dev/pci/cs4280.c intr = BA0READ4(sc, CS4280_HISR);
BA0READ4 795 dev/pci/cs4280.c BA0READ4(sc, CS4280_MIDSR)));
BA0READ4 798 dev/pci/cs4280.c ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) {
BA0READ4 799 dev/pci/cs4280.c data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK;
BA0READ4 810 dev/pci/cs4280.c if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
BA0READ4 817 dev/pci/cs4280.c ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) {
BA0READ4 993 dev/pci/cs4280.c while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) {
BA0READ4 1679 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE;
BA0READ4 1698 dev/pci/cs4280.c while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) {
BA0READ4 1712 dev/pci/cs4280.c while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) !=
BA0READ4 1803 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
BA0READ4 1805 dev/pci/cs4280.c DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
BA0READ4 1867 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_CLKCR1);
BA0READ4 1876 dev/pci/cs4280.c while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) {
BA0READ4 1908 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
BA0READ4 1912 dev/pci/cs4280.c if (mem != BA0READ4(sc, CS4280_MIDCR)) {
BA0READ4 1913 dev/pci/cs4280.c DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR)));
BA0READ4 1916 dev/pci/cs4280.c DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
BA0READ4 1929 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_MIDCR);
BA0READ4 1947 dev/pci/cs4280.c if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
BA0READ4 1948 dev/pci/cs4280.c mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK;
BA0READ4 1952 dev/pci/cs4280.c if (mem != BA0READ4(sc, CS4280_MIDWP)) {
BA0READ4 1954 dev/pci/cs4280.c mem, BA0READ4(sc, CS4280_MIDWP)));
BA0READ4 395 dev/pci/cs4281.c intr = BA0READ4(sc, CS4281_HISR);
BA0READ4 403 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
BA0READ4 405 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
BA0READ4 410 dev/pci/cs4281.c DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0),
BA0READ4 411 dev/pci/cs4281.c (int)BA0READ4(sc, CS4281_DCC0)));
BA0READ4 429 dev/pci/cs4281.c val = BA0READ4(sc, CS4281_HDSR1);
BA0READ4 431 dev/pci/cs4281.c DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1),
BA0READ4 432 dev/pci/cs4281.c (int)BA0READ4(sc, CS4281_DCC1)));
BA0READ4 588 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
BA0READ4 601 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
BA0READ4 645 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
BA0READ4 685 dev/pci/cs4281.c fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK;
BA0READ4 702 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK);
BA0READ4 709 dev/pci/cs4281.c DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR)));
BA0READ4 710 dev/pci/cs4281.c DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR)));
BA0READ4 711 dev/pci/cs4281.c DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0)));
BA0READ4 712 dev/pci/cs4281.c DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0)));
BA0READ4 713 dev/pci/cs4281.c DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0)));
BA0READ4 715 dev/pci/cs4281.c BA0READ4(sc, CS4281_DACSR)));
BA0READ4 716 dev/pci/cs4281.c DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA)));
BA0READ4 718 dev/pci/cs4281.c BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN));
BA0READ4 749 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
BA0READ4 778 dev/pci/cs4281.c fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK;
BA0READ4 795 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK);
BA0READ4 799 dev/pci/cs4281.c DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR)));
BA0READ4 800 dev/pci/cs4281.c DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR)));
BA0READ4 801 dev/pci/cs4281.c DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1)));
BA0READ4 802 dev/pci/cs4281.c DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1)));
BA0READ4 878 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_EPPMC);
BA0READ4 917 dev/pci/cs4281.c while ((BA0READ4(sc, CS4281_CLKCR1)& (CLKCR1_DLLRDY | CLKCR1_CLKON))
BA0READ4 929 dev/pci/cs4281.c while((BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY) == 0) {
BA0READ4 938 dev/pci/cs4281.c while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
BA0READ4 958 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY;
BA0READ4 989 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4);
BA0READ4 1043 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc,CS4281_FCR0) & ~FCRn_FEN));
BA0READ4 1064 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc,CS4281_FCR1) & ~FCRn_FEN));
BA0READ4 1087 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc,CS4281_FCR2) & ~FCRn_FEN));
BA0READ4 1088 dev/pci/cs4281.c BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc,CS4281_FCR3) & ~FCRn_FEN));
BA0READ4 1137 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_HIMR) & 0xfffbfcff;
BA0READ4 1213 dev/pci/cs4281.c while((BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY) == 0) {
BA0READ4 1223 dev/pci/cs4281.c while((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
BA0READ4 1242 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_ACSTS) & ACSTS_CRDY;
BA0READ4 1273 dev/pci/cs4281.c dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ;
BA0READ4 1472 dev/pci/cs4281.c BA0READ4(sc, CS4281_ACSDA);
BA0READ4 1489 dev/pci/cs4281.c while ((BA0READ4(sc, CS4281_ACSTS) & ACSTS_VSTS) == 0) {
BA0READ4 1497 dev/pci/cs4281.c *ac97_data = BA0READ4(sc, CS4281_ACSDA);
BA0READ4 1589 dev/pci/cs4281.c while ((BA0READ4(sc, CS4281_ACCTL) & ACCTL_DCV)) {