ad_write 153 dev/isa/ad1848.c static void ad_write(struct ad1848_softc *, int, int); ad_write 337 dev/isa/ad1848.c ad_write(sc, 0, 0xaa); ad_write 338 dev/isa/ad1848.c ad_write(sc, 1, 0x45); /* 0x55 with bit 0x10 clear */ ad_write 346 dev/isa/ad1848.c ad_write(sc, 0, 0x45); ad_write 347 dev/isa/ad1848.c ad_write(sc, 1, 0xaa); ad_write 360 dev/isa/ad1848.c ad_write(sc, SP_MISC_INFO, (~tmp) & 0x0f); ad_write 414 dev/isa/ad1848.c ad_write(sc, SP_MISC_INFO, 0); /* Mode2 = disabled */ ad_write 429 dev/isa/ad1848.c ad_write(sc, SP_MISC_INFO, MODE2); /* Set mode2, clear 0x80 */ ad_write 438 dev/isa/ad1848.c ad_write(sc, 18, 0x88); /* Set I18 to known value */ ad_write 440 dev/isa/ad1848.c ad_write(sc, 2, 0x45); ad_write 442 dev/isa/ad1848.c ad_write(sc, 2, 0xaa); ad_write 534 dev/isa/ad1848.c ad_write(sc, i, ad1848_init_values[i]); ad_write 541 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, 0); /* disable SINGLE_DMA */ ad_write 544 dev/isa/ad1848.c ad_write(sc, i, ad1848_init_values[i]); ad_write 618 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg & 0xFE); ad_write 620 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x80); ad_write 623 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg | 0x01); ad_write 625 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].left_reg, reg & ~0x80); ad_write 635 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].right_reg, reg | 0x80); ad_write 637 dev/isa/ad1848.c ad_write(sc, mixer_channel_info[device].right_reg, reg & ~0x80); ad_write 662 dev/isa/ad1848.c ad_write(sc, info->left_reg, reg); ad_write 670 dev/isa/ad1848.c ad_write(sc, info->right_reg, (atten& info->atten_bits)|reg); ad_write 709 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, (gain&0x0f)|reg); ad_write 714 dev/isa/ad1848.c ad_write(sc, SP_RIGHT_INPUT_CONTROL, (gain&0x0f)|reg); ad_write 750 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, reg | INPUT_MIC_GAIN_ENABLE); ad_write 754 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, reg & ~INPUT_MIC_GAIN_ENABLE); ad_write 1131 dev/isa/ad1848.c ad_write(sc, SP_LEFT_INPUT_CONTROL, (inp|reg)); ad_write 1135 dev/isa/ad1848.c ad_write(sc, SP_RIGHT_INPUT_CONTROL, (inp|reg)); ad_write 1179 dev/isa/ad1848.c ad_write(sc, SP_PIN_CONTROL, INTERRUPT_ENABLE|ad_read(sc, SP_PIN_CONTROL)); ad_write 1210 dev/isa/ad1848.c ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)0); ad_write 1211 dev/isa/ad1848.c ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)0); ad_write 1215 dev/isa/ad1848.c ad_write(sc, SP_PIN_CONTROL, ad_write 1221 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, r); ad_write 1255 dev/isa/ad1848.c ad_write(sc, SP_CLOCK_DATA_FORMAT, fs); ad_write 1273 dev/isa/ad1848.c ad_write(sc, CS_REC_FORMAT, fs); ad_write 1319 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, r); ad_write 1419 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~PLAYBACK_ENABLE)); ad_write 1435 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (reg & ~CAPTURE_ENABLE)); ad_write 1504 dev/isa/ad1848.c ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff)); ad_write 1505 dev/isa/ad1848.c ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff)); ad_write 1508 dev/isa/ad1848.c ad_write(sc, CS_LOWER_REC_CNT, (u_char)(cc & 0xff)); ad_write 1509 dev/isa/ad1848.c ad_write(sc, CS_UPPER_REC_CNT, (u_char)((cc >> 8) & 0xff)); ad_write 1513 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (CAPTURE_ENABLE|reg)); ad_write 1589 dev/isa/ad1848.c ad_write(sc, SP_LOWER_BASE_COUNT, (u_char)(cc & 0xff)); ad_write 1590 dev/isa/ad1848.c ad_write(sc, SP_UPPER_BASE_COUNT, (u_char)((cc >> 8) & 0xff)); ad_write 1593 dev/isa/ad1848.c ad_write(sc, SP_INTERFACE_CONFIG, (PLAYBACK_ENABLE|reg));