STE_PHYCTL        142 dev/pci/if_ste.c #define MII_SET(x)		STE_SETBIT1(sc, STE_PHYCTL, x)
STE_PHYCTL        143 dev/pci/if_ste.c #define MII_CLR(x)		STE_CLRBIT1(sc, STE_PHYCTL, x) 
STE_PHYCTL        214 dev/pci/if_ste.c 	CSR_WRITE_2(sc, STE_PHYCTL, 0);
STE_PHYCTL        242 dev/pci/if_ste.c 	ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
STE_PHYCTL        264 dev/pci/if_ste.c 			if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)