RISC_BLOCK        586 dev/ic/ispreg.h #define	RISC_ACC	RISC_BLOCK+0x0	/* RW*: Accumulator */
RISC_BLOCK        587 dev/ic/ispreg.h #define	RISC_R1		RISC_BLOCK+0x2	/* RW*: GP Reg R1  */
RISC_BLOCK        588 dev/ic/ispreg.h #define	RISC_R2		RISC_BLOCK+0x4	/* RW*: GP Reg R2  */
RISC_BLOCK        589 dev/ic/ispreg.h #define	RISC_R3		RISC_BLOCK+0x6	/* RW*: GP Reg R3  */
RISC_BLOCK        590 dev/ic/ispreg.h #define	RISC_R4		RISC_BLOCK+0x8	/* RW*: GP Reg R4  */
RISC_BLOCK        591 dev/ic/ispreg.h #define	RISC_R5		RISC_BLOCK+0xA	/* RW*: GP Reg R5  */
RISC_BLOCK        592 dev/ic/ispreg.h #define	RISC_R6		RISC_BLOCK+0xC	/* RW*: GP Reg R6  */
RISC_BLOCK        593 dev/ic/ispreg.h #define	RISC_R7		RISC_BLOCK+0xE	/* RW*: GP Reg R7  */
RISC_BLOCK        594 dev/ic/ispreg.h #define	RISC_R8		RISC_BLOCK+0x10	/* RW*: GP Reg R8  */
RISC_BLOCK        595 dev/ic/ispreg.h #define	RISC_R9		RISC_BLOCK+0x12	/* RW*: GP Reg R9  */
RISC_BLOCK        596 dev/ic/ispreg.h #define	RISC_R10	RISC_BLOCK+0x14	/* RW*: GP Reg R10 */
RISC_BLOCK        597 dev/ic/ispreg.h #define	RISC_R11	RISC_BLOCK+0x16	/* RW*: GP Reg R11 */
RISC_BLOCK        598 dev/ic/ispreg.h #define	RISC_R12	RISC_BLOCK+0x18	/* RW*: GP Reg R12 */
RISC_BLOCK        599 dev/ic/ispreg.h #define	RISC_R13	RISC_BLOCK+0x1a	/* RW*: GP Reg R13 */
RISC_BLOCK        600 dev/ic/ispreg.h #define	RISC_R14	RISC_BLOCK+0x1c	/* RW*: GP Reg R14 */
RISC_BLOCK        601 dev/ic/ispreg.h #define	RISC_R15	RISC_BLOCK+0x1e	/* RW*: GP Reg R15 */
RISC_BLOCK        602 dev/ic/ispreg.h #define	RISC_PSR	RISC_BLOCK+0x20	/* RW*: Processor Status */
RISC_BLOCK        603 dev/ic/ispreg.h #define	RISC_IVR	RISC_BLOCK+0x22	/* RW*: Interrupt Vector */
RISC_BLOCK        604 dev/ic/ispreg.h #define	RISC_PCR	RISC_BLOCK+0x24	/* RW*: Processor Ctrl */
RISC_BLOCK        605 dev/ic/ispreg.h #define	RISC_RAR0	RISC_BLOCK+0x26	/* RW*: Ram Address #0 */
RISC_BLOCK        606 dev/ic/ispreg.h #define	RISC_RAR1	RISC_BLOCK+0x28	/* RW*: Ram Address #1 */
RISC_BLOCK        607 dev/ic/ispreg.h #define	RISC_LCR	RISC_BLOCK+0x2a	/* RW*: Loop Counter */
RISC_BLOCK        608 dev/ic/ispreg.h #define	RISC_PC		RISC_BLOCK+0x2c	/* R  : Program Counter */
RISC_BLOCK        609 dev/ic/ispreg.h #define	RISC_MTR	RISC_BLOCK+0x2e	/* RW*: Memory Timing */
RISC_BLOCK        610 dev/ic/ispreg.h #define		RISC_MTR2100	RISC_BLOCK+0x30
RISC_BLOCK        612 dev/ic/ispreg.h #define	RISC_EMB	RISC_BLOCK+0x30	/* RW*: Ext Mem Boundary */
RISC_BLOCK        614 dev/ic/ispreg.h #define	RISC_SP		RISC_BLOCK+0x32	/* RW*: Stack Pointer */
RISC_BLOCK        615 dev/ic/ispreg.h #define	RISC_HRL	RISC_BLOCK+0x3e	/* R *: Hardware Rev Level */
RISC_BLOCK        616 dev/ic/ispreg.h #define	HCCR		RISC_BLOCK+0x40	/* RW : Host Command & Ctrl */
RISC_BLOCK        617 dev/ic/ispreg.h #define	BP0		RISC_BLOCK+0x42	/* RW : Processor Brkpt #0 */
RISC_BLOCK        618 dev/ic/ispreg.h #define	BP1		RISC_BLOCK+0x44	/* RW : Processor Brkpt #1 */
RISC_BLOCK        619 dev/ic/ispreg.h #define	TCR		RISC_BLOCK+0x46	/*  W : Test Control */
RISC_BLOCK        620 dev/ic/ispreg.h #define	TMR		RISC_BLOCK+0x48	/*  W : Test Mode */
RISC_BLOCK        463 dev/pci/isp_pci.c 	pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
RISC_BLOCK        249 dev/sbus/isp_sbus.c 	sbc->sbus_poff[RISC_BLOCK >> _BLK_REG_SHFT] = SBUS_RISC_REGS_OFF;