READ_REG_0        285 dev/pci/hifn7751.c 	    READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
READ_REG_0        286 dev/pci/hifn7751.c 	ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
READ_REG_0        450 dev/pci/hifn7751.c 		if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
READ_REG_0        628 dev/pci/hifn7751.c 	ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
READ_REG_0        637 dev/pci/hifn7751.c 	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
READ_REG_0        673 dev/pci/hifn7751.c 	encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
READ_REG_0        797 dev/pci/hifn7751.c 	pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
READ_REG_0        905 dev/pci/hifn7751.c 		cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
READ_REG_0       1699 dev/pci/hifn7751.c 		WRITE_REG_0(sc, HIFN_0_PUISR, READ_REG_0(sc, HIFN_0_PUISR));
READ_REG_0        138 dev/pci/lofn.c 	    READ_REG_0(sc, LOFN_REL_CFG2) | LOFN_CFG2_RNGENA);
READ_REG_0        144 dev/pci/lofn.c 	    READ_REG_0(sc, LOFN_REL_CFG2) | LOFN_CFG2_PRCENA);
READ_REG_0        176 dev/pci/lofn.c 	sr = READ_REG_0(sc, LOFN_REL_SR);
READ_REG_0        184 dev/pci/lofn.c 			    READ_REG_0(sc, LOFN_REL_CFG2) &