AR5K_AR5211_PHY   224 dev/ic/ar5211.c 	hal->ah_phy = AR5K_AR5211_PHY(0);
AR5K_AR5211_PHY   354 dev/ic/ar5211.c 		AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ);
AR5K_AR5211_PHY   357 dev/ic/ar5211.c 		AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
AR5K_AR5211_PHY   366 dev/ic/ar5211.c 	AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16);
AR5K_AR5211_PHY   369 dev/ic/ar5211.c 		AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000);
AR5K_AR5211_PHY   370 dev/ic/ar5211.c 	srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff;
AR5K_AR5211_PHY   375 dev/ic/ar5211.c 	AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
AR5K_AR5211_PHY   477 dev/ic/ar5211.c 	AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
AR5K_AR5211_PHY   529 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44),
AR5K_AR5211_PHY   546 dev/ic/ar5211.c 	AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a),
AR5K_AR5211_PHY   549 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11),
AR5K_AR5211_PHY   551 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12),
AR5K_AR5211_PHY   553 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14),
AR5K_AR5211_PHY   557 dev/ic/ar5211.c 	AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d),
AR5K_AR5211_PHY   563 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a),
AR5K_AR5211_PHY   565 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19),
AR5K_AR5211_PHY   567 dev/ic/ar5211.c 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01);