LGE_MODE1_SETRST_CTL0  366 dev/pci/if_lge.c 	LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
LGE_MODE1_SETRST_CTL0 1247 dev/pci/if_lge.c 	    LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
LGE_MODE1_SETRST_CTL0 1312 dev/pci/if_lge.c 	CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);