LGE_MODE1 328 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); LGE_MODE1 366 dev/pci/if_lge.c LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); LGE_MODE1 369 dev/pci/if_lge.c if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) LGE_MODE1 1245 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| LGE_MODE1 1252 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1 1255 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); LGE_MODE1 1262 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1 1265 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); LGE_MODE1 1269 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); LGE_MODE1 1272 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); LGE_MODE1 1275 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); LGE_MODE1 1278 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); LGE_MODE1 1279 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); LGE_MODE1 1282 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); LGE_MODE1 1285 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); LGE_MODE1 1288 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| LGE_MODE1 1312 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); LGE_MODE1 1316 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); LGE_MODE1 1319 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); LGE_MODE1 1403 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1 1410 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1 1490 dev/pci/if_lge.c CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);