ISP_WRITE 205 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); ISP_WRITE 239 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); ISP_WRITE 261 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS); ISP_WRITE 262 dev/ic/isp.c ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET); ISP_WRITE 263 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS); ISP_WRITE 264 dev/ic/isp.c ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL); ISP_WRITE 265 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS); ISP_WRITE 443 dev/ic/isp.c ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET); ISP_WRITE 452 dev/ic/isp.c ISP_WRITE(isp, CDMA_CONTROL, ISP_WRITE 454 dev/ic/isp.c ISP_WRITE(isp, DDMA_CONTROL, ISP_WRITE 459 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); ISP_WRITE 468 dev/ic/isp.c ISP_WRITE(isp, CDMA2100_CONTROL, ISP_WRITE 470 dev/ic/isp.c ISP_WRITE(isp, TDMA2100_CONTROL, ISP_WRITE 472 dev/ic/isp.c ISP_WRITE(isp, RDMA2100_CONTROL, ISP_WRITE 501 dev/ic/isp.c ISP_WRITE(isp, BIU_CONF1, 0); ISP_WRITE 503 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0); ISP_WRITE 509 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RESET); ISP_WRITE 512 dev/ic/isp.c ISP_WRITE(isp, BIU_SEMA, 0); ISP_WRITE 535 dev/ic/isp.c ISP_WRITE(isp, RISC_MTR, 0x1313); ISP_WRITE 536 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_STEP); ISP_WRITE 539 dev/ic/isp.c ISP_WRITE(isp, RISC_MTR, 0x1212); ISP_WRITE 544 dev/ic/isp.c ISP_WRITE(isp, RISC_EMB, DUAL_BANK) ISP_WRITE 546 dev/ic/isp.c ISP_WRITE(isp, RISC_MTR, 0x1212); ISP_WRITE 549 dev/ic/isp.c ISP_WRITE(isp, RISC_MTR2100, 0x1212); ISP_WRITE 551 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_2X00_DISABLE_PARITY_PAUSE); ISP_WRITE 555 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); /* release paused processor */ ISP_WRITE 865 dev/ic/isp.c ISP_WRITE(isp, RISC_MTR, 0x1313); ISP_WRITE 1347 dev/ic/isp.c ISP_WRITE(isp, isp->isp_rqstinrp, 0); ISP_WRITE 1348 dev/ic/isp.c ISP_WRITE(isp, isp->isp_rqstoutrp, 0); ISP_WRITE 1349 dev/ic/isp.c ISP_WRITE(isp, isp->isp_respinrp, 0); ISP_WRITE 1350 dev/ic/isp.c ISP_WRITE(isp, isp->isp_respoutrp, 0); ISP_WRITE 3526 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); ISP_WRITE 3527 dev/ic/isp.c ISP_WRITE(isp, BIU_SEMA, 0); ISP_WRITE 3544 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); ISP_WRITE 3545 dev/ic/isp.c ISP_WRITE(isp, BIU_SEMA, 0); ISP_WRITE 3581 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); ISP_WRITE 3626 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); ISP_WRITE 3627 dev/ic/isp.c ISP_WRITE(isp, BIU_SEMA, 0); ISP_WRITE 4755 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT); ISP_WRITE 4756 dev/ic/isp.c ISP_WRITE(isp, BIU_SEMA, 0); ISP_WRITE 5271 dev/ic/isp.c ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]); ISP_WRITE 5282 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); ISP_WRITE 5330 dev/ic/isp.c ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]); ISP_WRITE 5346 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT); ISP_WRITE 5937 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT); ISP_WRITE 5939 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK); ISP_WRITE 5968 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, bit); ISP_WRITE 5970 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, bit | BIU_NVRAM_CLOCK); ISP_WRITE 5972 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, bit); ISP_WRITE 5982 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK); ISP_WRITE 5989 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT); ISP_WRITE 5992 dev/ic/isp.c ISP_WRITE(isp, BIU_NVRAM, 0); ISP_WRITE 6420 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); ISP_WRITE 6452 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0); ISP_WRITE 6461 dev/ic/isp.c ISP_WRITE(isp, BIU_BLOCK + 0xA4, 0x2000 + (j << 8)); ISP_WRITE 6471 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x10); ISP_WRITE 6479 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x20); ISP_WRITE 6487 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x30); ISP_WRITE 6497 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); ISP_WRITE 6508 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); ISP_WRITE 6519 dev/ic/isp.c ISP_WRITE(isp, RISC_EMB, 0xf2); ISP_WRITE 6520 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); ISP_WRITE 6564 dev/ic/isp.c ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); ISP_WRITE 6597 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x40); ISP_WRITE 6605 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x50); ISP_WRITE 6613 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0); ISP_WRITE 6622 dev/ic/isp.c ISP_WRITE(isp, BIU_BLOCK + 0xA4, 0x2000 + (j << 9)); ISP_WRITE 6632 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x10); ISP_WRITE 6640 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x20); ISP_WRITE 6648 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, 0x30); ISP_WRITE 6658 dev/ic/isp.c ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET); ISP_WRITE 6689 dev/ic/isp.c ISP_WRITE(isp, PCI_MBOX_REGS2300_OFF + (8 << 1), 0x1); ISP_WRITE 238 dev/ic/ispmbox.h ISP_WRITE(isp, isp->isp_rqstinrp, value) ISP_WRITE 247 dev/ic/ispmbox.h ISP_WRITE(isp, isp->isp_respoutrp, value) ISP_WRITE 231 dev/ic/ispreg.h ISP_WRITE(isp, BIU_ICR, BIU_ICR_ENABLE_RISC_INT | BIU_ICR_ENABLE_ALL_INTS) : \ ISP_WRITE 232 dev/ic/ispreg.h ISP_WRITE(isp, BIU_ICR, BIU2100_ICR_ENA_RISC_INT | BIU2100_ICR_ENABLE_ALL_INTS) ISP_WRITE 239 dev/ic/ispreg.h #define DISABLE_INTS(isp) ISP_WRITE(isp, BIU_ICR, 0)